From 3c8616923a2f47beba2f9ebc2718e8880cd7820e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Philip=20M=C3=BCller?= <philm@manjaro.org>
Date: Tue, 22 Feb 2022 14:13:32 +0100
Subject: [PATCH] [pkg-upd] 2022.01-0.1 - use updated patches
---
...nitial-support-for-the-PinePhone-Pro.patch | 889 ----------------
...Correct-boot-order-to-be-USB-SD-eMMC.patch | 28 -
...nd-add-HS400-Enhanced-Strobe-support.patch | 959 ------------------
...USB-power-settings-for-PinePhone-Pro.patch | 228 +++++
...k-power-on-and-init-counts-in-uclass.patch | 430 ++++++++
...ci-Add-HS400-Enhanced-Strobe-support.patch | 84 ++
...ci-Fix-RK3399-eMMC-PHY-power-cycling.patch | 157 +++
...0-Enhanced-Strobe-support-for-RK3399.patch | 120 +++
...0-Enhanced-Strobe-support-for-RK3568.patch | 112 ++
PKGBUILD | 61 +-
10 files changed, 1170 insertions(+), 1898 deletions(-)
delete mode 100644 0001-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
delete mode 100644 0002-Correct-boot-order-to-be-USB-SD-eMMC.patch
delete mode 100644 0003-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch
create mode 100644 1003-Configure-USB-power-settings-for-PinePhone-Pro.patch
create mode 100644 2001-phy-Track-power-on-and-init-counts-in-uclass.patch
create mode 100644 2002-mmc-sdhci-Add-HS400-Enhanced-Strobe-support.patch
create mode 100644 2003-rockchip-sdhci-Fix-RK3399-eMMC-PHY-power-cycling.patch
create mode 100644 2004-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3399.patch
create mode 100644 2005-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3568.patch
diff --git a/0001-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch b/0001-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
deleted file mode 100644
index 3e48d2e..0000000
--- a/0001-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch
+++ /dev/null
@@ -1,889 +0,0 @@
-From eea38c80ff858222e15ba4d79a0cb811adbdfc23 Mon Sep 17 00:00:00 2001
-From: Martijn Braam <martijn@brixit.nl>
-Date: Sat, 12 Dec 2020 13:31:03 +0100
-Subject: [PATCH] rockchip: Add initial support for the PinePhone Pro
-
-This is a new device by PINE64 that's very similar to the Pinebook Pro
-that's already supported.
-
-Specification:
-- Rockchip RK3399
-- 4GB Dual-Channel LPDDR4
-- 128GB eMMC
-- mSD card slot
-- AP6255 for 802.11ac WiFi and Bluetooth
-- 6 inch 720*1440 DSI display
-- Quectel EG25g usb modem
-- Type-C port with alt-mode display (DP 1.2) and PD charging.
-
-Signed-off-by: Martijn Braam <martijn@brixit.nl>
----
- arch/arm/dts/Makefile | 1 +
- arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++
- arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++
- arch/arm/mach-rockchip/rk3399/Kconfig | 8 +
- board/pine64/pinephone-pro-rk3399/Kconfig | 15 +
- board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 +
- board/pine64/pinephone-pro-rk3399/Makefile | 1 +
- .../pinephone-pro-rk3399.c | 57 ++
- configs/pinephone-pro-rk3399_defconfig | 92 ++++
- include/configs/pinephone-pro-rk3399.h | 23 +
- 10 files changed, 769 insertions(+)
- create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
- create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts
- create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig
- create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS
- create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile
- create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
- create mode 100644 configs/pinephone-pro-rk3399_defconfig
- create mode 100644 include/configs/pinephone-pro-rk3399.h
-
-diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
-index aeaec713..6f123425 100644
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -145,6 +145,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
- rk3399-nanopi-r4s.dtb \
- rk3399-orangepi.dtb \
- rk3399-pinebook-pro.dtb \
-+ rk3399-pinephone-pro.dtb \
- rk3399-puma-haikou.dtb \
- rk3399-roc-pc.dtb \
- rk3399-roc-pc-mezzanine.dtb \
-diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
-new file mode 100644
-index 00000000..9d44db59
---- /dev/null
-+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
-@@ -0,0 +1,44 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com>
-+ * Copyright (C) 2021 Martijn Braam <martijn at brixit.nl>
-+ */
-+
-+#include "rk3399-u-boot.dtsi"
-+#include "rk3399-sdram-lpddr4-100.dtsi"
-+
-+/ {
-+ aliases {
-+ spi0 = &spi1;
-+ };
-+
-+ chosen {
-+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
-+ };
-+
-+ config {
-+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
-+ };
-+};
-+
-+&i2c0 {
-+ u-boot,dm-pre-reloc;
-+};
-+
-+&rk818 {
-+ u-boot,dm-pre-reloc;
-+};
-+
-+&rng {
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ max-frequency = <25000000>;
-+ u-boot,dm-pre-reloc;
-+};
-+
-+&sdmmc {
-+ max-frequency = <20000000>;
-+ u-boot,dm-pre-reloc;
-+};
-diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts
-new file mode 100644
-index 00000000..3fe1845c
---- /dev/null
-+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
-@@ -0,0 +1,520 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Martijn Braam <martijn@brixit.nl>
-+ */
-+
-+/dts-v1/;
-+#include "rk3399.dtsi"
-+#include "rk3399-opp.dtsi"
-+
-+/ {
-+ model = "Pine64 PinePhone Pro";
-+ compatible = "pine64,pinephone-pro", "rockchip,rk3399";
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ sdio_pwrseq: sdio-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ pinctrl-names = "default";
-+ };
-+
-+ /* Power tree */
-+ /* Root power source */
-+ vcc_sysin: vcc-sysin {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sysin";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ /* Main 3.3v supply */
-+ vcc3v3_sys: vcc3v3-sys {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc_sysin>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+};
-+
-+&cpu_l0 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l1 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l2 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_l3 {
-+ cpu-supply = <&vdd_cpu_l>;
-+};
-+
-+&cpu_b0 {
-+ cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&cpu_b1 {
-+ cpu-supply = <&vdd_cpu_b>;
-+};
-+
-+&emmc_phy {
-+ status = "okay";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ clock-frequency = <400000>;
-+ i2c-scl-rising-time-ns = <168>;
-+ i2c-scl-falling-time-ns = <4>;
-+ status = "okay";
-+
-+ rk818: pmic@1c {
-+ compatible = "rockchip,rk818";
-+ reg = <0x1c>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ clock-output-names = "xin32k", "rk808-clkout2";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>;
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc_sysin>;
-+ vcc2-supply = <&vcc_sysin>;
-+ vcc3-supply = <&vcc_sysin>;
-+ vcc4-supply = <&vcc_sysin>;
-+ vcc6-supply = <&vcc_sysin>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc_sysin>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+
-+ regulators {
-+ vdd_cpu_l: DCDC_REG1 {
-+ regulator-name = "vdd_cpu_1";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <750000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_center: DCDC_REG2 {
-+ regulator-name = "vdd_center";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG4 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca3v0_codec: LDO_REG1 {
-+ regulator-name = "vcca3v0_codec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v0_touch: LDO_REG2 {
-+ regulator-name = "vcc3v0_touch";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_codec: LDO_REG3 {
-+ regulator-name = "vcca1v8_codec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_power_on: LDO_REG4 {
-+ regulator-name = "vcc_power_on";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc_3v0: LDO_REG5 {
-+ regulator-name = "vcc_3v0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3000000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3000000>;
-+ };
-+ };
-+
-+ vcc_1v5: LDO_REG6 {
-+ regulator-name = "vcc_1v5";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1500000>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1500000>;
-+ };
-+ };
-+
-+ vcc1v8_dvp: LDO_REG7 {
-+ regulator-name = "vcc1v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_s3: LDO_REG8 {
-+ regulator-name = "vcc3v3_s3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_sd: LDO_REG9 {
-+ regulator-name = "vcc_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc3v3_s0: SWITCH_REG {
-+ regulator-name = "vcc3v3_s0";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ boost_otg: DCDC_BOOST {
-+ regulator-name = "boost_otg";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <5000000>;
-+ };
-+ };
-+
-+ otg_switch: OTG_SWITCH {
-+ regulator-name = "otg_switch";
-+ };
-+ };
-+ };
-+
-+ vdd_cpu_b: regulator@40 {
-+ compatible = "silergy,syr827";
-+ reg = <0x40>;
-+ fcs,suspend-voltage-selector = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vsel1_pin>;
-+ regulator-name = "vdd_cpu_b";
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-ramp-delay = <1000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: regulator@41 {
-+ compatible = "silergy,syr828";
-+ reg = <0x41>;
-+ fcs,suspend-voltage-selector = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vsel2_pin>;
-+ regulator-name = "vdd_gpu";
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-ramp-delay = <1000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+};
-+
-+&i2c1 {
-+ i2c-scl-rising-time-ns = <300>;
-+ i2c-scl-falling-time-ns = <15>;
-+ status = "okay";
-+};
-+
-+&i2c3 {
-+ i2c-scl-rising-time-ns = <450>;
-+ i2c-scl-falling-time-ns = <15>;
-+ status = "okay";
-+};
-+
-+&i2c4 {
-+ i2c-scl-rising-time-ns = <600>;
-+ i2c-scl-falling-time-ns = <20>;
-+ status = "okay";
-+
-+ fusb0: typec-portc@22 {
-+ compatible = "fcs,fusb302";
-+ reg = <0x22>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&fusb0_int>;
-+ status = "okay";
-+ };
-+};
-+
-+&io_domains {
-+ status = "okay";
-+
-+ bt656-supply = <&vcc1v8_dvp>;
-+ audio-supply = <&vcca1v8_codec>;
-+ sdmmc-supply = <&vcc_sd>;
-+ gpio1830-supply = <&vcc_3v0>;
-+};
-+
-+&pmu_io_domains {
-+ pmu1830-supply = <&vcc_3v0>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ bt {
-+ bt_enable_h: bt-enable-h {
-+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_host_wake_l: bt-host-wake-l {
-+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+
-+ bt_wake_l: bt-wake-l {
-+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ buttons {
-+ pwrbtn: pwrbtn {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ fusb302x {
-+ fusb0_int: fusb0-int {
-+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ leds {
-+ work_led_pin: work-led-pin {
-+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ diy_led_pin: diy-led-pin {
-+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie_perst: pcie-perst {
-+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie_pwr_en: pcie-pwr-en {
-+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+
-+ vsel1_pin: vsel1-pin {
-+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+
-+ vsel2_pin: vsel2-pin {
-+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+
-+ sdcard {
-+ sdmmc0_pwr_h: sdmmc0-pwr-h {
-+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ };
-+
-+ sdio-pwrseq {
-+ wifi_enable_h: wifi-enable-h {
-+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb-typec {
-+ vcc5v0_typec_en: vcc5v0_typec_en {
-+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb2 {
-+ vcc5v0_host_en: vcc5v0-host-en {
-+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pwm0 {
-+ status = "okay";
-+};
-+
-+&pwm1 {
-+ status = "okay";
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&sdio0 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ disable-wp;
-+ keep-power-in-suspend;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
-+ sd-uhs-sdr104;
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
-+ disable-wp;
-+ max-frequency = <150000000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
-+ vmmc-supply = <&vcc3v3_s3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ /* tshut mode 0:CRU 1:GPIO */
-+ rockchip,hw-tshut-mode = <1>;
-+ /* tshut polarity 0:LOW 1:HIGH */
-+ rockchip,hw-tshut-polarity = <1>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&vopb {
-+ status = "okay";
-+};
-+
-+&vopb_mmu {
-+ status = "okay";
-+};
-+
-+&vopl {
-+ status = "okay";
-+};
-+
-+&vopl_mmu {
-+ status = "okay";
-+};
-diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
-index 17628f91..3ba603ca 100644
---- a/arch/arm/mach-rockchip/rk3399/Kconfig
-+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
-@@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399
- with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port,
- 1920*1080 screen and all the usual laptop features.
-
-+config TARGET_PINEPHONE_PRO_RK3399
-+ bool "PinePhone Pro"
-+ help
-+ PinePhone Pro is a phone based on the Rockchip rk3399 SoC
-+ with 4Gb RAM, onboard eMMC, USB-C, a headphone jack,
-+ 720x1440 screen and an external Quectel USB modem.
-+
- config TARGET_PUMA_RK3399
- bool "Theobroma Systems RK3399-Q7 (Puma)"
- help
-@@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT
- source "board/firefly/roc-pc-rk3399/Kconfig"
- source "board/google/gru/Kconfig"
- source "board/pine64/pinebook-pro-rk3399/Kconfig"
-+source "board/pine64/pinephone-pro-rk3399/Kconfig"
- source "board/pine64/rockpro64_rk3399/Kconfig"
- source "board/rockchip/evb_rk3399/Kconfig"
- source "board/theobroma-systems/puma_rk3399/Kconfig"
-diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig
-new file mode 100644
-index 00000000..13d6465a
---- /dev/null
-+++ b/board/pine64/pinephone-pro-rk3399/Kconfig
-@@ -0,0 +1,15 @@
-+if TARGET_PINEPHONE_PRO_RK3399
-+
-+config SYS_BOARD
-+ default "pinephone-pro-rk3399"
-+
-+config SYS_VENDOR
-+ default "pine64"
-+
-+config SYS_CONFIG_NAME
-+ default "pinephone-pro-rk3399"
-+
-+config BOARD_SPECIFIC_OPTIONS
-+ def_bool y
-+
-+endif
-diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
-new file mode 100644
-index 00000000..9ca4fc4c
---- /dev/null
-+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
-@@ -0,0 +1,8 @@
-+PINEPHONE_PRO
-+M: Martijn Braam <martijn@brixit.nl>
-+S: Maintained
-+F: board/pine64/rk3399-pinephone-pro/
-+F: include/configs/rk3399-pinephone-pro.h
-+F: arch/arm/dts/rk3399-pinephone-pro.dts
-+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
-+F: configs/pinephone-pro-rk3399_defconfig
-diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile
-new file mode 100644
-index 00000000..8d920305
---- /dev/null
-+++ b/board/pine64/pinephone-pro-rk3399/Makefile
-@@ -0,0 +1 @@
-+obj-y += pinephone-pro-rk3399.o
-diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
-new file mode 100644
-index 00000000..8efeb6ea
---- /dev/null
-+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
-@@ -0,0 +1,57 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
-+ * (C) Copyright 2021 Martijn Braam <martijn@brixit.nl>
-+ */
-+
-+#include <common.h>
-+#include <dm.h>
-+#include <init.h>
-+#include <syscon.h>
-+#include <asm/io.h>
-+#include <asm/arch-rockchip/clock.h>
-+#include <asm/arch-rockchip/grf_rk3399.h>
-+#include <asm/arch-rockchip/hardware.h>
-+#include <asm/arch-rockchip/misc.h>
-+
-+#define GRF_IO_VSEL_BT565_SHIFT 0
-+#define PMUGRF_CON0_VSEL_SHIFT 8
-+
-+#ifdef CONFIG_MISC_INIT_R
-+static void setup_iodomain(void)
-+{
-+ struct rk3399_grf_regs *grf =
-+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-+ struct rk3399_pmugrf_regs *pmugrf =
-+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-+
-+ /* BT565 is in 1.8v domain */
-+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
-+
-+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
-+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
-+}
-+
-+int misc_init_r(void)
-+{
-+ const u32 cpuid_offset = 0x7;
-+ const u32 cpuid_length = 0x10;
-+ u8 cpuid[cpuid_length];
-+ int ret;
-+
-+ setup_iodomain();
-+
-+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
-+ if (ret)
-+ return ret;
-+
-+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
-+ if (ret)
-+ return ret;
-+
-+ ret = rockchip_setup_macaddr();
-+
-+ return ret;
-+}
-+
-+#endif
-diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
-new file mode 100644
-index 00000000..2cf80f7d
---- /dev/null
-+++ b/configs/pinephone-pro-rk3399_defconfig
-@@ -0,0 +1,92 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_SYS_TEXT_BASE=0x00200000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_ENV_SIZE=0x8000
-+CONFIG_ROCKCHIP_RK3399=y
-+CONFIG_TARGET_PINEPHONE_PRO_RK3399=y
-+CONFIG_DEBUG_UART_BASE=0xFF1A0000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-+CONFIG_SPL_SPI_SUPPORT=y
-+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
-+CONFIG_DEBUG_UART=y
-+CONFIG_SYS_LOAD_ADDR=0x800800
-+CONFIG_BOOTDELAY=3
-+CONFIG_USE_PREBOOT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+CONFIG_MISC_INIT_R=y
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
-+CONFIG_SPL_MTD_SUPPORT=y
-+CONFIG_SPL_SPI_LOAD=y
-+CONFIG_TPL=y
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_I2C=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_PCI=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_TIME=y
-+CONFIG_CMD_PMIC=y
-+CONFIG_CMD_REGULATOR=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_ENV_IS_IN_SPI_FLASH=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_DM_KEYBOARD=y
-+CONFIG_LED=y
-+CONFIG_LED_GPIO=y
-+CONFIG_MISC=y
-+CONFIG_ROCKCHIP_EFUSE=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_SDMA=y
-+CONFIG_MMC_SDHCI_ROCKCHIP=y
-+CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_SPI_FLASH_GIGADEVICE=y
-+CONFIG_SPI_FLASH_WINBOND=y
-+CONFIG_DM_ETH=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PHY_ROCKCHIP_TYPEC=y
-+CONFIG_DM_PMIC_FAN53555=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM_RK3399_LPDDR4=y
-+CONFIG_DM_RESET=y
-+CONFIG_DM_RNG=y
-+CONFIG_RNG_ROCKCHIP=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_ROCKCHIP_SPI=y
-+CONFIG_SYSRESET=y
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_XHCI_DWC3=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_GENERIC=y
-+CONFIG_USB_DWC3=y
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_USB_KEYBOARD=y
-+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
-+CONFIG_USB_HOST_ETHER=y
-+CONFIG_USB_ETHER_ASIX=y
-+CONFIG_USB_ETHER_RTL8152=y
-+CONFIG_DM_VIDEO=y
-+CONFIG_DISPLAY=y
-+CONFIG_VIDEO_ROCKCHIP=y
-+CONFIG_DISPLAY_ROCKCHIP_EDP=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y
-diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h
-new file mode 100644
-index 00000000..fefa793f
---- /dev/null
-+++ b/include/configs/pinephone-pro-rk3399.h
-@@ -0,0 +1,23 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+/*
-+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd
-+ * Copyright (C) 2020 Peter Robinson <pbrobinson at gmail.com>
-+ * Copyright (C) 2021 Martijn Braam <martijn@brixit.nl>
-+ */
-+
-+#ifndef __PINEPHONE_PRO_RK3399_H
-+#define __PINEPHONE_PRO_RK3399_H
-+
-+#define ROCKCHIP_DEVICE_SETTINGS \
-+ "stdin=serial,usbkbd\0" \
-+ "stdout=serial,vidconsole\0" \
-+ "stderr=serial,vidconsole\0"
-+
-+#include <configs/rk3399_common.h>
-+
-+#define SDRAM_BANK_SIZE (2UL << 30)
-+
-+#define CONFIG_USB_OHCI_NEW
-+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-+
-+#endif
---
-2.34.1
-
diff --git a/0002-Correct-boot-order-to-be-USB-SD-eMMC.patch b/0002-Correct-boot-order-to-be-USB-SD-eMMC.patch
deleted file mode 100644
index 5b218b5..0000000
--- a/0002-Correct-boot-order-to-be-USB-SD-eMMC.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From f97401137daa1cb75532c373bbcb5011f1e03585 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Sun, 10 Oct 2021 20:19:02 +0200
-Subject: [PATCH] Correct boot order to be USB -> SD -> eMMC
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- include/configs/rockchip-common.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
-index ba7061a287..5dc92373b2 100644
---- a/include/configs/rockchip-common.h
-+++ b/include/configs/rockchip-common.h
-@@ -55,9 +55,9 @@
-
- #ifdef CONFIG_ROCKCHIP_RK3399
- #define BOOT_TARGET_DEVICES(func) \
-+ BOOT_TARGET_USB(func) \
- BOOT_TARGET_MMC(func) \
- BOOT_TARGET_NVME(func) \
-- BOOT_TARGET_USB(func) \
- BOOT_TARGET_PXE(func) \
- BOOT_TARGET_DHCP(func) \
- BOOT_TARGET_SF(func)
---
-2.33.0
-
diff --git a/0003-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch b/0003-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch
deleted file mode 100644
index fdd0a71..0000000
--- a/0003-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch
+++ /dev/null
@@ -1,959 +0,0 @@
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-From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-To: u-boot@lists.denx.de
-Cc: Aswath Govindraju <a-govindraju@ti.com>,
- Kever Yang <kever.yang@rock-chips.com>,
- Philipp Tomsich <philipp.tomsich@vrull.eu>,
- Samuel Dionne-Riel <samuel@dionne-riel.com>,
- Stephen Carlson <stcarlso@linux.microsoft.com>,
- Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
- Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
- Jaehoon Chung <jh80.chung@samsung.com>,
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- Jagan Teki <jagan@amarulasolutions.com>,
- Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Subject: [PATCH v3 1/4] mmc: sdhci: Add HS400 Enhanced Strobe support
-Date: Sun, 16 Jan 2022 23:18:10 +0300
-Message-Id: <20220116201814.11672-2-alpernebiyasak@gmail.com>
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-
-Delegate setting the Enhanced Strobe configuration to individual drivers
-if they set a function for it. Return -ENOTSUPP if they do not, like
-what the MMC uclass does.
-
-Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
----
-
-(no changes since v2)
-
-Changes in v2:
-- Add tag: "Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>"
-
- drivers/mmc/sdhci.c | 18 ++++++++++++++++++
- include/sdhci.h | 1 +
- 2 files changed, 19 insertions(+)
-
-diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
-index 766e4a6b0c5e..bf989a594f7e 100644
---- a/drivers/mmc/sdhci.c
-+++ b/drivers/mmc/sdhci.c
-@@ -513,6 +513,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
- reg |= SDHCI_CTRL_UHS_SDR104;
- break;
- case MMC_HS_400:
-+ case MMC_HS_400_ES:
- reg |= SDHCI_CTRL_HS400;
- break;
- default:
-@@ -666,6 +667,7 @@ static int sdhci_set_ios(struct mmc *mmc)
- mmc->selected_mode == MMC_DDR_52 ||
- mmc->selected_mode == MMC_HS_200 ||
- mmc->selected_mode == MMC_HS_400 ||
-+ mmc->selected_mode == MMC_HS_400_ES ||
- mmc->selected_mode == UHS_SDR25 ||
- mmc->selected_mode == UHS_SDR50 ||
- mmc->selected_mode == UHS_SDR104 ||
-@@ -799,6 +801,19 @@ static int sdhci_wait_dat0(struct udevice *dev, int state,
- return -ETIMEDOUT;
- }
-
-+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
-+static int sdhci_set_enhanced_strobe(struct udevice *dev)
-+{
-+ struct mmc *mmc = mmc_get_mmc_dev(dev);
-+ struct sdhci_host *host = mmc->priv;
-+
-+ if (host->ops && host->ops->set_enhanced_strobe)
-+ return host->ops->set_enhanced_strobe(host);
-+
-+ return -ENOTSUPP;
-+}
-+#endif
-+
- const struct dm_mmc_ops sdhci_ops = {
- .send_cmd = sdhci_send_command,
- .set_ios = sdhci_set_ios,
-@@ -808,6 +823,9 @@ const struct dm_mmc_ops sdhci_ops = {
- .execute_tuning = sdhci_execute_tuning,
- #endif
- .wait_dat0 = sdhci_wait_dat0,
-+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
-+ .set_enhanced_strobe = sdhci_set_enhanced_strobe,
-+#endif
- };
- #else
- static const struct mmc_ops sdhci_ops = {
-diff --git a/include/sdhci.h b/include/sdhci.h
-index c718dd7206c1..7a65fdf95d30 100644
---- a/include/sdhci.h
-+++ b/include/sdhci.h
-@@ -272,6 +272,7 @@ struct sdhci_ops {
- int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
- int (*set_delay)(struct sdhci_host *host);
- int (*deferred_probe)(struct sdhci_host *host);
-+ int (*set_enhanced_strobe)(struct sdhci_host *host);
- };
-
- #define ADMA_MAX_LEN 65532
-
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- Sun, 16 Jan 2022 12:18:35 -0800 (PST)
-From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-To: u-boot@lists.denx.de
-Cc: Aswath Govindraju <a-govindraju@ti.com>,
- Kever Yang <kever.yang@rock-chips.com>,
- Philipp Tomsich <philipp.tomsich@vrull.eu>,
- Samuel Dionne-Riel <samuel@dionne-riel.com>,
- Stephen Carlson <stcarlso@linux.microsoft.com>,
- Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
- Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
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- Jagan Teki <jagan@amarulasolutions.com>,
- Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Subject: [PATCH v3 2/4] rockchip: sdhci: Fix RK3399 eMMC PHY power cycling
-Date: Sun, 16 Jan 2022 23:18:11 +0300
-Message-Id: <20220116201814.11672-3-alpernebiyasak@gmail.com>
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-
-The Rockchip RK3399 eMMC PHY has to be power-cycled while changing its
-clock speed to some higher speeds. This is dependent on the desired
-SDHCI clock speed, and it looks like the PHY should be powered off while
-setting the SDHCI clock in these cases.
-
-Commit ac804143cfd1 ("mmc: rockchip_sdhci: add phy and clock config for
-rk3399") attempts to do this in the set_ios_post() hook by setting the
-SDHCI clock once more while the PHY is turned off/on as necessary, as
-the SDHCI framework does not provide a way to override how it sets its
-clock. However, the commit breaks reinitializing the eMMC on a few
-boards including chromebook_kevin and reportedly ROCKPro64.
-
-This patch reworks the power cycling to utilize the SDHCI framework
-slightly better (using the set_control_reg() hook to power off the PHY
-and set_ios_post() hook to power it back on) which happens to fix the
-issue, at least on a chromebook_kevin.
-
-Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
----
-RK3568 parts only build-tested as I don't have a RK3568 board.
-
-(no changes since v2)
-
-Changes in v2:
-- Add this patch
-
- drivers/mmc/rockchip_sdhci.c | 53 +++++++++++++++++++++++++++++-------
- 1 file changed, 43 insertions(+), 10 deletions(-)
-
-diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
-index 278473899c7c..f0d7ba4774d6 100644
---- a/drivers/mmc/rockchip_sdhci.c
-+++ b/drivers/mmc/rockchip_sdhci.c
-@@ -90,9 +90,10 @@ struct rockchip_sdhc {
- };
-
- struct sdhci_data {
-- int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
- int (*emmc_phy_init)(struct udevice *dev);
- int (*get_phy)(struct udevice *dev);
-+ void (*set_control_reg)(struct sdhci_host *host);
-+ int (*set_ios_post)(struct sdhci_host *host);
- };
-
- static int rk3399_emmc_phy_init(struct udevice *dev)
-@@ -182,15 +183,28 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
- return 0;
- }
-
--static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
-+static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
- {
- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-+ struct mmc *mmc = host->mmc;
-+ uint clock = mmc->tran_speed;
- int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
-
- if (cycle_phy)
- rk3399_emmc_phy_power_off(priv->phy);
-
-- sdhci_set_clock(host->mmc, clock);
-+ sdhci_set_control_reg(host);
-+};
-+
-+static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
-+{
-+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-+ struct mmc *mmc = host->mmc;
-+ uint clock = mmc->tran_speed;
-+ int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
-+
-+ if (!clock)
-+ clock = mmc->clock;
-
- if (cycle_phy)
- rk3399_emmc_phy_power_on(priv->phy, clock);
-@@ -269,10 +283,8 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
- return 0;
- }
-
--static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
-+static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
- {
-- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-- struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
- struct mmc *mmc = host->mmc;
- uint clock = mmc->tran_speed;
- u32 reg;
-@@ -280,8 +292,7 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
- if (!clock)
- clock = mmc->clock;
-
-- if (data->emmc_set_clock)
-- data->emmc_set_clock(host, clock);
-+ rk3568_sdhci_emmc_set_clock(host, clock);
-
- if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
- reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-@@ -295,6 +306,26 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
- return 0;
- }
-
-+static void rockchip_sdhci_set_control_reg(struct sdhci_host *host)
-+{
-+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-+ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
-+
-+ if (data->set_control_reg)
-+ data->set_control_reg(host);
-+}
-+
-+static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
-+{
-+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-+ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
-+
-+ if (data->set_ios_post)
-+ return data->set_ios_post(host);
-+
-+ return 0;
-+}
-+
- static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
- {
- struct sdhci_host *host = dev_get_priv(mmc->dev);
-@@ -358,6 +389,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
- static struct sdhci_ops rockchip_sdhci_ops = {
- .set_ios_post = rockchip_sdhci_set_ios_post,
- .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
-+ .set_control_reg = rockchip_sdhci_set_control_reg,
- };
-
- static int rockchip_sdhci_probe(struct udevice *dev)
-@@ -436,15 +468,16 @@ static int rockchip_sdhci_bind(struct udevice *dev)
- }
-
- static const struct sdhci_data rk3399_data = {
-- .emmc_set_clock = rk3399_sdhci_emmc_set_clock,
- .get_phy = rk3399_emmc_get_phy,
- .emmc_phy_init = rk3399_emmc_phy_init,
-+ .set_control_reg = rk3399_sdhci_set_control_reg,
-+ .set_ios_post = rk3399_sdhci_set_ios_post,
- };
-
- static const struct sdhci_data rk3568_data = {
-- .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
- .get_phy = rk3568_emmc_get_phy,
- .emmc_phy_init = rk3568_emmc_phy_init,
-+ .set_ios_post = rk3568_sdhci_set_ios_post,
- };
-
- static const struct udevice_id sdhci_ids[] = {
-
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- Sun, 16 Jan 2022 12:18:39 -0800 (PST)
-From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-To: u-boot@lists.denx.de
-Cc: Aswath Govindraju <a-govindraju@ti.com>,
- Kever Yang <kever.yang@rock-chips.com>,
- Philipp Tomsich <philipp.tomsich@vrull.eu>,
- Samuel Dionne-Riel <samuel@dionne-riel.com>,
- Stephen Carlson <stcarlso@linux.microsoft.com>,
- Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
- Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
- Jaehoon Chung <jh80.chung@samsung.com>,
- Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>,
- Michal Simek <michal.simek@xilinx.com>, Peng Fan <peng.fan@nxp.com>,
- Yifeng Zhao <yifeng.zhao@rock-chips.com>,
- Jagan Teki <jagan@amarulasolutions.com>,
- Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Subject: [PATCH v3 3/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for
- RK3399
-Date: Sun, 16 Jan 2022 23:18:12 +0300
-Message-Id: <20220116201814.11672-4-alpernebiyasak@gmail.com>
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-
-On RK3399, a register bit must be set to enable Enhanced Strobe.
-Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration
-is requested. However, having it set makes the lower-speed modes stop
-working and makes reinitialization fail, so let it be unset as needed in
-set_control_reg().
-
-This is mostly ported from Linux's Arasan SDHCI driver which happens
-to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux
-tree).
-
-Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
----
-
-(no changes since v2)
-
-Changes in v2:
-- Unset ES bit in rk3399 set_control_reg() to fix a reinit issue
-- Don't use unnecessary & for function pointer in ops struct
-- Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe
-- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
-
- drivers/mmc/rockchip_sdhci.c | 41 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
-diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
-index f0d7ba4774d6..f920c5141142 100644
---- a/drivers/mmc/rockchip_sdhci.c
-+++ b/drivers/mmc/rockchip_sdhci.c
-@@ -42,6 +42,9 @@
- ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
- PHYCTRL_DLLRDY_DONE)
-
-+#define ARASAN_VENDOR_REGISTER 0x78
-+#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
-+
- /* Rockchip specific Registers */
- #define DWCMSHC_EMMC_DLL_CTRL 0x800
- #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
-@@ -94,6 +97,7 @@ struct sdhci_data {
- int (*get_phy)(struct udevice *dev);
- void (*set_control_reg)(struct sdhci_host *host);
- int (*set_ios_post)(struct sdhci_host *host);
-+ int (*set_enhanced_strobe)(struct sdhci_host *host);
- };
-
- static int rk3399_emmc_phy_init(struct udevice *dev)
-@@ -183,6 +187,21 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
- return 0;
- }
-
-+static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
-+{
-+ struct mmc *mmc = host->mmc;
-+ u32 vendor;
-+
-+ vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
-+ if (mmc->selected_mode == MMC_HS_400_ES)
-+ vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
-+ else
-+ vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
-+ sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
-+
-+ return 0;
-+}
-+
- static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
- {
- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-@@ -194,6 +213,15 @@ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
- rk3399_emmc_phy_power_off(priv->phy);
-
- sdhci_set_control_reg(host);
-+
-+ /*
-+ * Reinitializing the device tries to set it to lower-speed modes
-+ * first, which fails if the Enhanced Strobe bit is set, making
-+ * the device impossible to use. Set the correct value here to
-+ * let reinitialization attempts succeed.
-+ */
-+ if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
-+ rk3399_sdhci_set_enhanced_strobe(host);
- };
-
- static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
-@@ -386,10 +414,22 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
- return ret;
- }
-
-+static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
-+{
-+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
-+ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
-+
-+ if (data->set_enhanced_strobe)
-+ return data->set_enhanced_strobe(host);
-+
-+ return -ENOTSUPP;
-+}
-+
- static struct sdhci_ops rockchip_sdhci_ops = {
- .set_ios_post = rockchip_sdhci_set_ios_post,
- .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
- .set_control_reg = rockchip_sdhci_set_control_reg,
-+ .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
- };
-
- static int rockchip_sdhci_probe(struct udevice *dev)
-@@ -472,6 +512,7 @@ static const struct sdhci_data rk3399_data = {
- .emmc_phy_init = rk3399_emmc_phy_init,
- .set_control_reg = rk3399_sdhci_set_control_reg,
- .set_ios_post = rk3399_sdhci_set_ios_post,
-+ .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
- };
-
- static const struct sdhci_data rk3568_data = {
-
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- Sun, 16 Jan 2022 12:18:44 -0800 (PST)
-From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-To: u-boot@lists.denx.de
-Cc: Aswath Govindraju <a-govindraju@ti.com>,
- Kever Yang <kever.yang@rock-chips.com>,
- Philipp Tomsich <philipp.tomsich@vrull.eu>,
- Samuel Dionne-Riel <samuel@dionne-riel.com>,
- Stephen Carlson <stcarlso@linux.microsoft.com>,
- Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
- Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
- Jaehoon Chung <jh80.chung@samsung.com>,
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- Yifeng Zhao <yifeng.zhao@rock-chips.com>,
- Jagan Teki <jagan@amarulasolutions.com>,
- Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Subject: [PATCH v3 4/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for
- RK3568
-Date: Sun, 16 Jan 2022 23:18:13 +0300
-Message-Id: <20220116201814.11672-5-alpernebiyasak@gmail.com>
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-
-On RK3568, a register bit must be set to enable Enhanced Strobe.
-However, it appears that the address of this register may differ from
-vendor to vendor and should be read from the underlying MMC IP. Let the
-Rockchip SDHCI driver read this address and set the relevant bit when
-Enhanced Strobe configuration is requested.
-
-Additionally, a bit signifying that the connected hardware is an eMMC
-chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also
-make the driver set this bit as appropriate.
-
-This is partly ported from Linux's Synopsys DWC MSHC driver which
-happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in
-Linux tree).
-
-Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
----
-Only build-tested as I don't have a RK3568 board.
-
-Changes in v3:
-- Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()
-
-Changes in v2:
-- Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
-- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
-
- drivers/mmc/rockchip_sdhci.c | 42 ++++++++++++++++++++++++++++++++++++
- 1 file changed, 42 insertions(+)
-
-diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
-index f920c5141142..4c7cc7535e2e 100644
---- a/drivers/mmc/rockchip_sdhci.c
-+++ b/drivers/mmc/rockchip_sdhci.c
-@@ -45,6 +45,14 @@
- #define ARASAN_VENDOR_REGISTER 0x78
- #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
-
-+/* DWC IP vendor area 1 pointer */
-+#define DWCMSHC_P_VENDOR_AREA1 0xe8
-+#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
-+/* Offset inside the vendor area 1 */
-+#define DWCMSHC_EMMC_CONTROL 0x2c
-+#define DWCMSHC_CARD_IS_EMMC BIT(0)
-+#define DWCMSHC_ENHANCED_STROBE BIT(8)
-+
- /* Rockchip specific Registers */
- #define DWCMSHC_EMMC_DLL_CTRL 0x800
- #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
-@@ -244,11 +252,25 @@ static int rk3568_emmc_phy_init(struct udevice *dev)
- {
- struct rockchip_sdhc *prv = dev_get_priv(dev);
- struct sdhci_host *host = &prv->host;
-+ struct mmc *mmc = host->mmc;
- u32 extra;
-+ u32 vendor;
-+ int reg;
-
- extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
-
-+ /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 and HS400ES */
-+ reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
-+ + DWCMSHC_EMMC_CONTROL;
-+
-+ vendor = sdhci_readw(host, reg);
-+ if (IS_MMC(mmc))
-+ vendor |= DWCMSHC_CARD_IS_EMMC;
-+ else
-+ vendor &= ~DWCMSHC_CARD_IS_EMMC;
-+ sdhci_writew(host, vendor, reg);
-+
- return 0;
- }
-
-@@ -311,6 +333,25 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
- return 0;
- }
-
-+static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
-+{
-+ struct mmc *mmc = host->mmc;
-+ u32 vendor;
-+ int reg;
-+
-+ reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
-+ + DWCMSHC_EMMC_CONTROL;
-+
-+ vendor = sdhci_readl(host, reg);
-+ if (mmc->selected_mode == MMC_HS_400_ES)
-+ vendor |= DWCMSHC_ENHANCED_STROBE;
-+ else
-+ vendor &= ~DWCMSHC_ENHANCED_STROBE;
-+ sdhci_writel(host, vendor, reg);
-+
-+ return 0;
-+}
-+
- static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
- {
- struct mmc *mmc = host->mmc;
-@@ -519,6 +560,7 @@ static const struct sdhci_data rk3568_data = {
- .get_phy = rk3568_emmc_get_phy,
- .emmc_phy_init = rk3568_emmc_phy_init,
- .set_ios_post = rk3568_sdhci_set_ios_post,
-+ .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
- };
-
- static const struct udevice_id sdhci_ids[] = {
diff --git a/1003-Configure-USB-power-settings-for-PinePhone-Pro.patch b/1003-Configure-USB-power-settings-for-PinePhone-Pro.patch
new file mode 100644
index 0000000..d2eb998
--- /dev/null
+++ b/1003-Configure-USB-power-settings-for-PinePhone-Pro.patch
@@ -0,0 +1,228 @@
+From 8ee2257dda6bed2f1ae117e614637036003785d4 Mon Sep 17 00:00:00 2001
+From: Dragan Simic <dragan.simic@gmail.com>
+Date: Thu, 30 Dec 2021 00:08:51 +0100
+Subject: [PATCH] Configure USB power settings for PinePhone Pro
+
+---
+ arch/arm/mach-rockchip/rk3399/rk3399.c | 5 ++
+ .../pinephone-pro-rk3399.c | 58 ++++++++++++++++---
+ configs/pinephone-pro-rk3399_defconfig | 6 ++
+ drivers/power/regulator/rk8xx.c | 21 ++++---
+ 4 files changed, 72 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
+index d40969c8..644e4ab2 100644
+--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
++++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
+@@ -248,9 +248,14 @@ void __weak led_setup(void)
+ {
+ }
+
++void __weak power_setup(void)
++{
++}
++
+ void spl_board_init(void)
+ {
+ led_setup();
++ power_setup();
+
+ #if defined(SPL_GPIO)
+ struct rockchip_cru *cru = rockchip_get_cru();
+diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+index 8efeb6ea..88583e31 100644
+--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
++++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+@@ -2,8 +2,14 @@
+ /*
+ * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
+ * (C) Copyright 2021 Martijn Braam <martijn@brixit.nl>
++ * (C) Copyright 2021 Dragan Simic <dsimic@buserror.io>
+ */
+
++/*
++ * TODO: Disable debugging
++ */
++#define DEBUG
++
+ #include <common.h>
+ #include <dm.h>
+ #include <init.h>
+@@ -13,6 +19,8 @@
+ #include <asm/arch-rockchip/grf_rk3399.h>
+ #include <asm/arch-rockchip/hardware.h>
+ #include <asm/arch-rockchip/misc.h>
++#include <power/regulator.h>
++#include <power/rk8xx_pmic.h>
+
+ #define GRF_IO_VSEL_BT565_SHIFT 0
+ #define PMUGRF_CON0_VSEL_SHIFT 8
+@@ -20,15 +28,13 @@
+ #ifdef CONFIG_MISC_INIT_R
+ static void setup_iodomain(void)
+ {
+- struct rk3399_grf_regs *grf =
+- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+- struct rk3399_pmugrf_regs *pmugrf =
+- syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
++ struct rk3399_grf_regs *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++ struct rk3399_pmugrf_regs *pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+- /* BT565 is in 1.8v domain */
++ /* BT565 is in 1.8 V domain */
+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
+
+- /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
++ /* Set GPIO1 1.8/3.0 V source select to PMU1830_VOL */
+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
+ }
+
+@@ -53,5 +59,43 @@ int misc_init_r(void)
+
+ return ret;
+ }
++#endif /* CONFIG_MISC_INIT_R */
+
+-#endif
++/*
++ * TODO: Change CONFIG_SPL_POWER_SUPPORT to CONFIG_SPL_POWER, to match newer U-Boot versions.
++ * The same applies to CONFIG_SPL_I2C_SUPPORT.
++ */
++
++#if defined(CONFIG_SPL_BUILD) && \
++ CONFIG_IS_ENABLED(POWER_SUPPORT) && !CONFIG_IS_ENABLED(OF_PLATDATA)
++static int setup_usb_power(void)
++{
++ struct udevice *pmic;
++ int ret;
++
++ ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
++ if (ret)
++ return ret;
++
++ /* set USB current limit to 2.5 A */
++ ret = rk818_spl_configure_usb_input_current(pmic, 2500);
++ if (ret)
++ return ret;
++
++ /* set USB low voltage threshold to 3.26 V */
++ ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++void power_setup(void)
++{
++ int ret;
++
++ ret = setup_usb_power();
++ if (ret)
++ debug("Failed to configure USB power settings: %d\n", ret);
++}
++#endif /* CONFIG_SPL_BUILD && POWER_SUPPORT && !OF_PLATDATA */
+diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
+index 2cf80f7d..b7ca9317 100644
+--- a/configs/pinephone-pro-rk3399_defconfig
++++ b/configs/pinephone-pro-rk3399_defconfig
+@@ -23,6 +23,11 @@ CONFIG_SPL_STACK_R=y
+ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+ CONFIG_SPL_MTD_SUPPORT=y
+ CONFIG_SPL_SPI_LOAD=y
++CONFIG_SPL_I2C_SUPPORT=y
++CONFIG_SPL_POWER_SUPPORT=y
++CONFIG_SPL_GPIO_SUPPORT=y
++CONFIG_SPL_DM=y
++CONFIG_SPL_DM_REGULATOR=y
+ CONFIG_TPL=y
+ CONFIG_CMD_BOOTZ=y
+ CONFIG_CMD_GPIO=y
+@@ -34,6 +39,7 @@ CONFIG_CMD_USB=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_TIME=y
+ CONFIG_CMD_PMIC=y
++# CONFIG_SPL_PMIC_CHILDREN is not set
+ CONFIG_CMD_REGULATOR=y
+ CONFIG_SPL_OF_CONTROL=y
+ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
+index 0ee07ad2..9d42a6ca 100644
+--- a/drivers/power/regulator/rk8xx.c
++++ b/drivers/power/regulator/rk8xx.c
+@@ -16,14 +16,10 @@
+ #include <power/pmic.h>
+ #include <power/regulator.h>
+
+-#ifndef CONFIG_SPL_BUILD
+-#define ENABLE_DRIVER
+-#endif
+-
+ /* Not used or exisit register and configure */
+ #define NA 0xff
+
+-/* Field Definitions */
++/* Field definitions */
+ #define RK808_BUCK_VSEL_MASK 0x3f
+ #define RK808_BUCK4_VSEL_MASK 0xf
+ #define RK808_LDO_VSEL_MASK 0x1f
+@@ -145,7 +141,7 @@ static const struct rk8xx_reg_info rk818_buck[] = {
+ { 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
+ };
+
+-#ifdef ENABLE_DRIVER
++#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+ static const struct rk8xx_reg_info rk808_ldo[] = {
+ { 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
+ { 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
+@@ -206,8 +202,9 @@ static const struct rk8xx_reg_info rk818_ldo[] = {
+ { 800000, 100000, REG_LDO7_ON_VSEL, REG_LDO7_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
+ { 1800000, 100000, REG_LDO8_ON_VSEL, REG_LDO8_SLP_VSEL, NA, RK818_LDO_VSEL_MASK, },
+ };
+-#endif
++#endif /* PMIC_CHILDREN */
+
++#ifdef CONFIG_SPL_BUILD
+ static const u16 rk818_chrg_cur_input_array[] = {
+ 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
+ };
+@@ -215,6 +212,7 @@ static const u16 rk818_chrg_cur_input_array[] = {
+ static const uint rk818_chrg_shutdown_vsel_array[] = {
+ 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
+ };
++#endif /* CONFIG_SPL_BUILD */
+
+ static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
+ int num, int uvolt)
+@@ -357,7 +355,7 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
+ return ret;
+ }
+
+-#ifdef ENABLE_DRIVER
++#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
+ static int _buck_set_suspend_value(struct udevice *pmic, int buck, int uvolt)
+ {
+ const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck, uvolt);
+@@ -1121,8 +1119,9 @@ U_BOOT_DRIVER(rk8xx_switch) = {
+ .ops = &rk8xx_switch_ops,
+ .probe = rk8xx_switch_probe,
+ };
+-#endif
++#endif /* PMIC_CHILDREN */
+
++#ifdef CONFIG_SPL_BUILD
+ int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
+ {
+ int ret;
+@@ -1153,6 +1152,6 @@ int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
+ if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
+ break;
+
+- return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
+- i);
++ return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, i);
+ }
++#endif /* CONFIG_SPL_BUILD */
+--
+2.34.1
+
diff --git a/2001-phy-Track-power-on-and-init-counts-in-uclass.patch b/2001-phy-Track-power-on-and-init-counts-in-uclass.patch
new file mode 100644
index 0000000..d0283bc
--- /dev/null
+++ b/2001-phy-Track-power-on-and-init-counts-in-uclass.patch
@@ -0,0 +1,430 @@
+From 226fce6108fe364e35f3eb9a84ff1a7ec93727ce Mon Sep 17 00:00:00 2001
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Date: Thu, 30 Dec 2021 22:36:51 +0300
+Subject: [PATCH] phy: Track power-on and init counts in uclass
+
+On boards using the RK3399 SoC, the USB OHCI and EHCI controllers share
+the same PHY device instance. While these controllers are being stopped
+they both attempt to power-off and deinitialize it, but trying to
+power-off the deinitialized PHY device results in a hang. This usually
+happens just before booting an OS, and can be explicitly triggered by
+running "usb start; usb stop" in the U-Boot shell.
+
+Implement a uclass-wide counting mechanism for PHY initialization and
+power state change requests, so that we don't power-off/deinitialize a
+PHY instance until all of its users want it done. The Allwinner A10 USB
+PHY driver does this counting in-driver, remove those parts in favour of
+this in-uclass implementation.
+
+The sandbox PHY operations test needs some changes since the uclass will
+no longer call into the drivers for actions matching its tracked state
+(e.g. powering-off a powered-off PHY). Update that test, and add a new
+one which simulates multiple users of a single PHY.
+
+The major complication here is that PHY handles aren't deduplicated per
+instance, so the obvious idea of putting the counts in the PHY handles
+don't immediately work. It seems possible to bind a child udevice per
+PHY instance to the PHY provider and deduplicate the handles in each
+child's uclass-private areas, like in the CLK framework. An alternative
+approach could be to use those bound child udevices themselves as the
+PHY handles. Instead, to avoid the architectural changes those would
+require, this patch solves things by dynamically allocating a list of
+structs (one per instance) in the provider's uclass-private area.
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Tested-by: Peter Robinson <pbrobinson@gmail.com> - Rock960
+---
+ drivers/phy/allwinner/phy-sun4i-usb.c | 9 --
+ drivers/phy/phy-uclass.c | 137 ++++++++++++++++++++++++++
+ test/dm/phy.c | 83 +++++++++++++++-
+ 3 files changed, 215 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index ab2a5d17fc..86c589a65f 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -125,7 +125,6 @@ struct sun4i_usb_phy_info {
+
+ struct sun4i_usb_phy_plat {
+ void __iomem *pmu;
+- int power_on_count;
+ int gpio_vbus;
+ int gpio_vbus_det;
+ int gpio_id_det;
+@@ -225,10 +224,6 @@ static int sun4i_usb_phy_power_on(struct phy *phy)
+ initial_usb_scan_delay = 0;
+ }
+
+- usb_phy->power_on_count++;
+- if (usb_phy->power_on_count != 1)
+- return 0;
+-
+ if (usb_phy->gpio_vbus >= 0)
+ gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
+
+@@ -240,10 +235,6 @@ static int sun4i_usb_phy_power_off(struct phy *phy)
+ struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
+ struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+
+- usb_phy->power_on_count--;
+- if (usb_phy->power_on_count != 0)
+- return 0;
+-
+ if (usb_phy->gpio_vbus >= 0)
+ gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
+
+diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
+index 706e9fdf3a..49e2ec25c2 100644
+--- a/drivers/phy/phy-uclass.c
++++ b/drivers/phy/phy-uclass.c
+@@ -11,12 +11,96 @@
+ #include <dm/device_compat.h>
+ #include <dm/devres.h>
+ #include <generic-phy.h>
++#include <linux/list.h>
++
++/**
++ * struct phy_counts - Init and power-on counts of a single PHY port
++ *
++ * This structure is used to keep track of PHY initialization and power
++ * state change requests, so that we don't power off and deinitialize a
++ * PHY instance until all of its users want it done. Otherwise, multiple
++ * consumers using the same PHY port can cause problems (e.g. one might
++ * call power_off() after another's exit() and hang indefinitely).
++ *
++ * @id: The PHY ID within a PHY provider
++ * @power_on_count: Times generic_phy_power_on() was called for this ID
++ * without a matching generic_phy_power_off() afterwards
++ * @init_count: Times generic_phy_init() was called for this ID
++ * without a matching generic_phy_exit() afterwards
++ * @list: Handle for a linked list of these structures corresponding to
++ * ports of the same PHY provider
++ */
++struct phy_counts {
++ unsigned long id;
++ int power_on_count;
++ int init_count;
++ struct list_head list;
++};
+
+ static inline struct phy_ops *phy_dev_ops(struct udevice *dev)
+ {
+ return (struct phy_ops *)dev->driver->ops;
+ }
+
++static struct phy_counts *phy_get_counts(struct phy *phy)
++{
++ struct list_head *uc_priv;
++ struct phy_counts *counts;
++
++ if (!generic_phy_valid(phy))
++ return NULL;
++
++ uc_priv = dev_get_uclass_priv(phy->dev);
++ list_for_each_entry(counts, uc_priv, list)
++ if (counts->id == phy->id)
++ return counts;
++
++ return NULL;
++}
++
++static int phy_alloc_counts(struct phy *phy)
++{
++ struct list_head *uc_priv;
++ struct phy_counts *counts;
++
++ if (!generic_phy_valid(phy))
++ return 0;
++ if (phy_get_counts(phy))
++ return 0;
++
++ uc_priv = dev_get_uclass_priv(phy->dev);
++ counts = kzalloc(sizeof(*counts), GFP_KERNEL);
++ if (!counts)
++ return -ENOMEM;
++
++ counts->id = phy->id;
++ counts->power_on_count = 0;
++ counts->init_count = 0;
++ list_add(&counts->list, uc_priv);
++
++ return 0;
++}
++
++static int phy_uclass_pre_probe(struct udevice *dev)
++{
++ struct list_head *uc_priv = dev_get_uclass_priv(dev);
++
++ INIT_LIST_HEAD(uc_priv);
++
++ return 0;
++}
++
++static int phy_uclass_pre_remove(struct udevice *dev)
++{
++ struct list_head *uc_priv = dev_get_uclass_priv(dev);
++ struct phy_counts *counts, *next;
++
++ list_for_each_entry_safe(counts, next, uc_priv, list)
++ kfree(counts);
++
++ return 0;
++}
++
+ static int generic_phy_xlate_offs_flags(struct phy *phy,
+ struct ofnode_phandle_args *args)
+ {
+@@ -88,6 +172,12 @@ int generic_phy_get_by_index_nodev(ofnode node, int index, struct phy *phy)
+ goto err;
+ }
+
++ ret = phy_alloc_counts(phy);
++ if (ret) {
++ debug("phy_alloc_counts() failed: %d\n", ret);
++ goto err;
++ }
++
+ return 0;
+
+ err:
+@@ -118,6 +208,7 @@ int generic_phy_get_by_name(struct udevice *dev, const char *phy_name,
+
+ int generic_phy_init(struct phy *phy)
+ {
++ struct phy_counts *counts;
+ struct phy_ops const *ops;
+ int ret;
+
+@@ -126,10 +217,19 @@ int generic_phy_init(struct phy *phy)
+ ops = phy_dev_ops(phy->dev);
+ if (!ops->init)
+ return 0;
++
++ counts = phy_get_counts(phy);
++ if (counts->init_count > 0) {
++ counts->init_count++;
++ return 0;
++ }
++
+ ret = ops->init(phy);
+ if (ret)
+ dev_err(phy->dev, "PHY: Failed to init %s: %d.\n",
+ phy->dev->name, ret);
++ else
++ counts->init_count = 1;
+
+ return ret;
+ }
+@@ -154,6 +254,7 @@ int generic_phy_reset(struct phy *phy)
+
+ int generic_phy_exit(struct phy *phy)
+ {
++ struct phy_counts *counts;
+ struct phy_ops const *ops;
+ int ret;
+
+@@ -162,16 +263,28 @@ int generic_phy_exit(struct phy *phy)
+ ops = phy_dev_ops(phy->dev);
+ if (!ops->exit)
+ return 0;
++
++ counts = phy_get_counts(phy);
++ if (counts->init_count == 0)
++ return 0;
++ if (counts->init_count > 1) {
++ counts->init_count--;
++ return 0;
++ }
++
+ ret = ops->exit(phy);
+ if (ret)
+ dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n",
+ phy->dev->name, ret);
++ else
++ counts->init_count = 0;
+
+ return ret;
+ }
+
+ int generic_phy_power_on(struct phy *phy)
+ {
++ struct phy_counts *counts;
+ struct phy_ops const *ops;
+ int ret;
+
+@@ -180,16 +293,26 @@ int generic_phy_power_on(struct phy *phy)
+ ops = phy_dev_ops(phy->dev);
+ if (!ops->power_on)
+ return 0;
++
++ counts = phy_get_counts(phy);
++ if (counts->power_on_count > 0) {
++ counts->power_on_count++;
++ return 0;
++ }
++
+ ret = ops->power_on(phy);
+ if (ret)
+ dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n",
+ phy->dev->name, ret);
++ else
++ counts->power_on_count = 1;
+
+ return ret;
+ }
+
+ int generic_phy_power_off(struct phy *phy)
+ {
++ struct phy_counts *counts;
+ struct phy_ops const *ops;
+ int ret;
+
+@@ -198,10 +321,21 @@ int generic_phy_power_off(struct phy *phy)
+ ops = phy_dev_ops(phy->dev);
+ if (!ops->power_off)
+ return 0;
++
++ counts = phy_get_counts(phy);
++ if (counts->power_on_count == 0)
++ return 0;
++ if (counts->power_on_count > 1) {
++ counts->power_on_count--;
++ return 0;
++ }
++
+ ret = ops->power_off(phy);
+ if (ret)
+ dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n",
+ phy->dev->name, ret);
++ else
++ counts->power_on_count = 0;
+
+ return ret;
+ }
+@@ -316,4 +450,7 @@ int generic_phy_power_off_bulk(struct phy_bulk *bulk)
+ UCLASS_DRIVER(phy) = {
+ .id = UCLASS_PHY,
+ .name = "phy",
++ .pre_probe = phy_uclass_pre_probe,
++ .pre_remove = phy_uclass_pre_remove,
++ .per_device_auto = sizeof(struct list_head),
+ };
+diff --git a/test/dm/phy.c b/test/dm/phy.c
+index ecbd47bf12..df4c73fc70 100644
+--- a/test/dm/phy.c
++++ b/test/dm/phy.c
+@@ -79,12 +79,15 @@ static int dm_test_phy_ops(struct unit_test_state *uts)
+ ut_assertok(generic_phy_power_off(&phy1));
+
+ /*
+- * test operations after exit().
+- * The sandbox phy driver does not allow it.
++ * Test power_on() failure after exit().
++ * The sandbox phy driver does not allow power-on/off after
++ * exit, but the uclass counts power-on/init calls and skips
++ * calling the driver's ops when e.g. powering off an already
++ * powered-off phy.
+ */
+ ut_assertok(generic_phy_exit(&phy1));
+ ut_assert(generic_phy_power_on(&phy1) != 0);
+- ut_assert(generic_phy_power_off(&phy1) != 0);
++ ut_assertok(generic_phy_power_off(&phy1));
+
+ /*
+ * test normal operations again (after re-init)
+@@ -99,6 +102,17 @@ static int dm_test_phy_ops(struct unit_test_state *uts)
+ */
+ ut_assertok(generic_phy_reset(&phy1));
+
++ /*
++ * Test power_off() failure after exit().
++ * For this we need to call exit() while the phy is powered-on,
++ * so that the uclass actually calls the driver's power-off()
++ * and reports the resulting failure.
++ */
++ ut_assertok(generic_phy_power_on(&phy1));
++ ut_assertok(generic_phy_exit(&phy1));
++ ut_assert(generic_phy_power_off(&phy1) != 0);
++ ut_assertok(generic_phy_power_on(&phy1));
++
+ /* PHY2 has a known problem with power off */
+ ut_assertok(generic_phy_init(&phy2));
+ ut_assertok(generic_phy_power_on(&phy2));
+@@ -106,8 +120,8 @@ static int dm_test_phy_ops(struct unit_test_state *uts)
+
+ /* PHY3 has a known problem with power off and power on */
+ ut_assertok(generic_phy_init(&phy3));
+- ut_asserteq(-EIO, generic_phy_power_off(&phy3));
+- ut_asserteq(-EIO, generic_phy_power_off(&phy3));
++ ut_asserteq(-EIO, generic_phy_power_on(&phy3));
++ ut_assertok(generic_phy_power_off(&phy3));
+
+ return 0;
+ }
+@@ -145,3 +159,62 @@ static int dm_test_phy_bulk(struct unit_test_state *uts)
+ return 0;
+ }
+ DM_TEST(dm_test_phy_bulk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
++
++static int dm_test_phy_multi_exit(struct unit_test_state *uts)
++{
++ struct phy phy1_method1;
++ struct phy phy1_method2;
++ struct phy phy1_method3;
++ struct udevice *parent;
++
++ /* Get the same phy instance in 3 different ways. */
++ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS,
++ "gen_phy_user", &parent));
++ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method1));
++ ut_asserteq(0, phy1_method1.id);
++ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method2));
++ ut_asserteq(0, phy1_method2.id);
++ ut_asserteq_ptr(phy1_method1.dev, phy1_method1.dev);
++
++ ut_assertok(uclass_get_device_by_name(UCLASS_SIMPLE_BUS,
++ "gen_phy_user1", &parent));
++ ut_assertok(generic_phy_get_by_name(parent, "phy1", &phy1_method3));
++ ut_asserteq(0, phy1_method3.id);
++ ut_asserteq_ptr(phy1_method1.dev, phy1_method3.dev);
++
++ /*
++ * Test using the same PHY from different handles.
++ * In non-test code these could be in different drivers.
++ */
++
++ /*
++ * These must only call the driver's ops at the first init()
++ * and power_on().
++ */
++ ut_assertok(generic_phy_init(&phy1_method1));
++ ut_assertok(generic_phy_init(&phy1_method2));
++ ut_assertok(generic_phy_power_on(&phy1_method1));
++ ut_assertok(generic_phy_power_on(&phy1_method2));
++ ut_assertok(generic_phy_init(&phy1_method3));
++ ut_assertok(generic_phy_power_on(&phy1_method3));
++
++ /*
++ * These must not call the driver's ops as other handles still
++ * want the PHY powered-on and initialized.
++ */
++ ut_assertok(generic_phy_power_off(&phy1_method3));
++ ut_assertok(generic_phy_exit(&phy1_method3));
++
++ /*
++ * We would get an error here if the generic_phy_exit() above
++ * actually called the driver's exit(), as the sandbox driver
++ * doesn't allow power-off() after exit().
++ */
++ ut_assertok(generic_phy_power_off(&phy1_method1));
++ ut_assertok(generic_phy_power_off(&phy1_method2));
++ ut_assertok(generic_phy_exit(&phy1_method1));
++ ut_assertok(generic_phy_exit(&phy1_method2));
++
++ return 0;
++}
++DM_TEST(dm_test_phy_multi_exit, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+--
+2.33.1
+
diff --git a/2002-mmc-sdhci-Add-HS400-Enhanced-Strobe-support.patch b/2002-mmc-sdhci-Add-HS400-Enhanced-Strobe-support.patch
new file mode 100644
index 0000000..8d54f14
--- /dev/null
+++ b/2002-mmc-sdhci-Add-HS400-Enhanced-Strobe-support.patch
@@ -0,0 +1,84 @@
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Subject: [PATCH v3 1/4] mmc: sdhci: Add HS400 Enhanced Strobe support
+Date: Sun, 16 Jan 2022 23:18:10 +0300
+
+Delegate setting the Enhanced Strobe configuration to individual drivers
+if they set a function for it. Return -ENOTSUPP if they do not, like
+what the MMC uclass does.
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
+---
+
+(no changes since v2)
+
+Changes in v2:
+- Add tag: "Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>"
+
+ drivers/mmc/sdhci.c | 18 ++++++++++++++++++
+ include/sdhci.h | 1 +
+ 2 files changed, 19 insertions(+)
+
+diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
+index 766e4a6b0c5e..bf989a594f7e 100644
+--- a/drivers/mmc/sdhci.c
++++ b/drivers/mmc/sdhci.c
+@@ -513,6 +513,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
+ reg |= SDHCI_CTRL_UHS_SDR104;
+ break;
+ case MMC_HS_400:
++ case MMC_HS_400_ES:
+ reg |= SDHCI_CTRL_HS400;
+ break;
+ default:
+@@ -666,6 +667,7 @@ static int sdhci_set_ios(struct mmc *mmc)
+ mmc->selected_mode == MMC_DDR_52 ||
+ mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400 ||
++ mmc->selected_mode == MMC_HS_400_ES ||
+ mmc->selected_mode == UHS_SDR25 ||
+ mmc->selected_mode == UHS_SDR50 ||
+ mmc->selected_mode == UHS_SDR104 ||
+@@ -799,6 +801,19 @@ static int sdhci_wait_dat0(struct udevice *dev, int state,
+ return -ETIMEDOUT;
+ }
+
++#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
++static int sdhci_set_enhanced_strobe(struct udevice *dev)
++{
++ struct mmc *mmc = mmc_get_mmc_dev(dev);
++ struct sdhci_host *host = mmc->priv;
++
++ if (host->ops && host->ops->set_enhanced_strobe)
++ return host->ops->set_enhanced_strobe(host);
++
++ return -ENOTSUPP;
++}
++#endif
++
+ const struct dm_mmc_ops sdhci_ops = {
+ .send_cmd = sdhci_send_command,
+ .set_ios = sdhci_set_ios,
+@@ -808,6 +823,9 @@ const struct dm_mmc_ops sdhci_ops = {
+ .execute_tuning = sdhci_execute_tuning,
+ #endif
+ .wait_dat0 = sdhci_wait_dat0,
++#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
++ .set_enhanced_strobe = sdhci_set_enhanced_strobe,
++#endif
+ };
+ #else
+ static const struct mmc_ops sdhci_ops = {
+diff --git a/include/sdhci.h b/include/sdhci.h
+index c718dd7206c1..7a65fdf95d30 100644
+--- a/include/sdhci.h
++++ b/include/sdhci.h
+@@ -272,6 +272,7 @@ struct sdhci_ops {
+ int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+ int (*set_delay)(struct sdhci_host *host);
+ int (*deferred_probe)(struct sdhci_host *host);
++ int (*set_enhanced_strobe)(struct sdhci_host *host);
+ };
+
+ #define ADMA_MAX_LEN 65532
diff --git a/2003-rockchip-sdhci-Fix-RK3399-eMMC-PHY-power-cycling.patch b/2003-rockchip-sdhci-Fix-RK3399-eMMC-PHY-power-cycling.patch
new file mode 100644
index 0000000..9f98650
--- /dev/null
+++ b/2003-rockchip-sdhci-Fix-RK3399-eMMC-PHY-power-cycling.patch
@@ -0,0 +1,157 @@
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Subject: [PATCH v3 2/4] rockchip: sdhci: Fix RK3399 eMMC PHY power cycling
+Date: Sun, 16 Jan 2022 23:18:11 +0300
+
+The Rockchip RK3399 eMMC PHY has to be power-cycled while changing its
+clock speed to some higher speeds. This is dependent on the desired
+SDHCI clock speed, and it looks like the PHY should be powered off while
+setting the SDHCI clock in these cases.
+
+Commit ac804143cfd1 ("mmc: rockchip_sdhci: add phy and clock config for
+rk3399") attempts to do this in the set_ios_post() hook by setting the
+SDHCI clock once more while the PHY is turned off/on as necessary, as
+the SDHCI framework does not provide a way to override how it sets its
+clock. However, the commit breaks reinitializing the eMMC on a few
+boards including chromebook_kevin and reportedly ROCKPro64.
+
+This patch reworks the power cycling to utilize the SDHCI framework
+slightly better (using the set_control_reg() hook to power off the PHY
+and set_ios_post() hook to power it back on) which happens to fix the
+issue, at least on a chromebook_kevin.
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+---
+RK3568 parts only build-tested as I don't have a RK3568 board.
+
+(no changes since v2)
+
+Changes in v2:
+- Add this patch
+
+ drivers/mmc/rockchip_sdhci.c | 53 +++++++++++++++++++++++++++++-------
+ 1 file changed, 43 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
+index 278473899c7c..f0d7ba4774d6 100644
+--- a/drivers/mmc/rockchip_sdhci.c
++++ b/drivers/mmc/rockchip_sdhci.c
+@@ -90,9 +90,10 @@ struct rockchip_sdhc {
+ };
+
+ struct sdhci_data {
+- int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
+ int (*emmc_phy_init)(struct udevice *dev);
+ int (*get_phy)(struct udevice *dev);
++ void (*set_control_reg)(struct sdhci_host *host);
++ int (*set_ios_post)(struct sdhci_host *host);
+ };
+
+ static int rk3399_emmc_phy_init(struct udevice *dev)
+@@ -182,15 +183,28 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
+-static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
++static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
+ {
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct mmc *mmc = host->mmc;
++ uint clock = mmc->tran_speed;
+ int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
+
+ if (cycle_phy)
+ rk3399_emmc_phy_power_off(priv->phy);
+
+- sdhci_set_clock(host->mmc, clock);
++ sdhci_set_control_reg(host);
++};
++
++static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct mmc *mmc = host->mmc;
++ uint clock = mmc->tran_speed;
++ int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
++
++ if (!clock)
++ clock = mmc->clock;
+
+ if (cycle_phy)
+ rk3399_emmc_phy_power_on(priv->phy, clock);
+@@ -269,10 +283,8 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
+-static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
++static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
+ {
+- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+- struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+ struct mmc *mmc = host->mmc;
+ uint clock = mmc->tran_speed;
+ u32 reg;
+@@ -280,8 +292,7 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
+ if (!clock)
+ clock = mmc->clock;
+
+- if (data->emmc_set_clock)
+- data->emmc_set_clock(host, clock);
++ rk3568_sdhci_emmc_set_clock(host, clock);
+
+ if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+@@ -295,6 +306,26 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
+ return 0;
+ }
+
++static void rockchip_sdhci_set_control_reg(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
++
++ if (data->set_control_reg)
++ data->set_control_reg(host);
++}
++
++static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
++
++ if (data->set_ios_post)
++ return data->set_ios_post(host);
++
++ return 0;
++}
++
+ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+ {
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+@@ -358,6 +389,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+ static struct sdhci_ops rockchip_sdhci_ops = {
+ .set_ios_post = rockchip_sdhci_set_ios_post,
+ .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
++ .set_control_reg = rockchip_sdhci_set_control_reg,
+ };
+
+ static int rockchip_sdhci_probe(struct udevice *dev)
+@@ -436,15 +468,16 @@ static int rockchip_sdhci_bind(struct udevice *dev)
+ }
+
+ static const struct sdhci_data rk3399_data = {
+- .emmc_set_clock = rk3399_sdhci_emmc_set_clock,
+ .get_phy = rk3399_emmc_get_phy,
+ .emmc_phy_init = rk3399_emmc_phy_init,
++ .set_control_reg = rk3399_sdhci_set_control_reg,
++ .set_ios_post = rk3399_sdhci_set_ios_post,
+ };
+
+ static const struct sdhci_data rk3568_data = {
+- .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
+ .get_phy = rk3568_emmc_get_phy,
+ .emmc_phy_init = rk3568_emmc_phy_init,
++ .set_ios_post = rk3568_sdhci_set_ios_post,
+ };
+
+ static const struct udevice_id sdhci_ids[] = {
diff --git a/2004-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3399.patch b/2004-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3399.patch
new file mode 100644
index 0000000..21ea2ce
--- /dev/null
+++ b/2004-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3399.patch
@@ -0,0 +1,120 @@
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Subject: [PATCH v3 3/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399
+Date: Sun, 16 Jan 2022 23:18:12 +0300
+
+On RK3399, a register bit must be set to enable Enhanced Strobe.
+Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration
+is requested. However, having it set makes the lower-speed modes stop
+working and makes reinitialization fail, so let it be unset as needed in
+set_control_reg().
+
+This is mostly ported from Linux's Arasan SDHCI driver which happens
+to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux
+tree).
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+---
+
+(no changes since v2)
+
+Changes in v2:
+- Unset ES bit in rk3399 set_control_reg() to fix a reinit issue
+- Don't use unnecessary & for function pointer in ops struct
+- Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe
+- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
+
+ drivers/mmc/rockchip_sdhci.c | 41 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
+index f0d7ba4774d6..f920c5141142 100644
+--- a/drivers/mmc/rockchip_sdhci.c
++++ b/drivers/mmc/rockchip_sdhci.c
+@@ -42,6 +42,9 @@
+ ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
+ PHYCTRL_DLLRDY_DONE)
+
++#define ARASAN_VENDOR_REGISTER 0x78
++#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
++
+ /* Rockchip specific Registers */
+ #define DWCMSHC_EMMC_DLL_CTRL 0x800
+ #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
+@@ -94,6 +97,7 @@ struct sdhci_data {
+ int (*get_phy)(struct udevice *dev);
+ void (*set_control_reg)(struct sdhci_host *host);
+ int (*set_ios_post)(struct sdhci_host *host);
++ int (*set_enhanced_strobe)(struct sdhci_host *host);
+ };
+
+ static int rk3399_emmc_phy_init(struct udevice *dev)
+@@ -183,6 +187,21 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
++static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
++{
++ struct mmc *mmc = host->mmc;
++ u32 vendor;
++
++ vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
++ if (mmc->selected_mode == MMC_HS_400_ES)
++ vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
++ else
++ vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
++ sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
++
++ return 0;
++}
++
+ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
+ {
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+@@ -194,6 +213,15 @@ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
+ rk3399_emmc_phy_power_off(priv->phy);
+
+ sdhci_set_control_reg(host);
++
++ /*
++ * Reinitializing the device tries to set it to lower-speed modes
++ * first, which fails if the Enhanced Strobe bit is set, making
++ * the device impossible to use. Set the correct value here to
++ * let reinitialization attempts succeed.
++ */
++ if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
++ rk3399_sdhci_set_enhanced_strobe(host);
+ };
+
+ static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
+@@ -386,10 +414,22 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+ return ret;
+ }
+
++static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
++
++ if (data->set_enhanced_strobe)
++ return data->set_enhanced_strobe(host);
++
++ return -ENOTSUPP;
++}
++
+ static struct sdhci_ops rockchip_sdhci_ops = {
+ .set_ios_post = rockchip_sdhci_set_ios_post,
+ .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
+ .set_control_reg = rockchip_sdhci_set_control_reg,
++ .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
+ };
+
+ static int rockchip_sdhci_probe(struct udevice *dev)
+@@ -472,6 +512,7 @@ static const struct sdhci_data rk3399_data = {
+ .emmc_phy_init = rk3399_emmc_phy_init,
+ .set_control_reg = rk3399_sdhci_set_control_reg,
+ .set_ios_post = rk3399_sdhci_set_ios_post,
++ .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
+ };
+
+ static const struct sdhci_data rk3568_data = {
diff --git a/2005-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3568.patch b/2005-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3568.patch
new file mode 100644
index 0000000..45a5c36
--- /dev/null
+++ b/2005-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3568.patch
@@ -0,0 +1,112 @@
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Subject: [PATCH v3 4/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568
+Date: Sun, 16 Jan 2022 23:18:13 +0300
+
+On RK3568, a register bit must be set to enable Enhanced Strobe.
+However, it appears that the address of this register may differ from
+vendor to vendor and should be read from the underlying MMC IP. Let the
+Rockchip SDHCI driver read this address and set the relevant bit when
+Enhanced Strobe configuration is requested.
+
+Additionally, a bit signifying that the connected hardware is an eMMC
+chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also
+make the driver set this bit as appropriate.
+
+This is partly ported from Linux's Synopsys DWC MSHC driver which
+happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in
+Linux tree).
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+---
+Only build-tested as I don't have a RK3568 board.
+
+Changes in v3:
+- Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()
+
+Changes in v2:
+- Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
+- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
+
+ drivers/mmc/rockchip_sdhci.c | 42 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
+index f920c5141142..4c7cc7535e2e 100644
+--- a/drivers/mmc/rockchip_sdhci.c
++++ b/drivers/mmc/rockchip_sdhci.c
+@@ -45,6 +45,14 @@
+ #define ARASAN_VENDOR_REGISTER 0x78
+ #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
+
++/* DWC IP vendor area 1 pointer */
++#define DWCMSHC_P_VENDOR_AREA1 0xe8
++#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
++/* Offset inside the vendor area 1 */
++#define DWCMSHC_EMMC_CONTROL 0x2c
++#define DWCMSHC_CARD_IS_EMMC BIT(0)
++#define DWCMSHC_ENHANCED_STROBE BIT(8)
++
+ /* Rockchip specific Registers */
+ #define DWCMSHC_EMMC_DLL_CTRL 0x800
+ #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
+@@ -244,11 +252,25 @@ static int rk3568_emmc_phy_init(struct udevice *dev)
+ {
+ struct rockchip_sdhc *prv = dev_get_priv(dev);
+ struct sdhci_host *host = &prv->host;
++ struct mmc *mmc = host->mmc;
+ u32 extra;
++ u32 vendor;
++ int reg;
+
+ extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+
++ /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 and HS400ES */
++ reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
++ + DWCMSHC_EMMC_CONTROL;
++
++ vendor = sdhci_readw(host, reg);
++ if (IS_MMC(mmc))
++ vendor |= DWCMSHC_CARD_IS_EMMC;
++ else
++ vendor &= ~DWCMSHC_CARD_IS_EMMC;
++ sdhci_writew(host, vendor, reg);
++
+ return 0;
+ }
+
+@@ -311,6 +333,25 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
++static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
++{
++ struct mmc *mmc = host->mmc;
++ u32 vendor;
++ int reg;
++
++ reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
++ + DWCMSHC_EMMC_CONTROL;
++
++ vendor = sdhci_readl(host, reg);
++ if (mmc->selected_mode == MMC_HS_400_ES)
++ vendor |= DWCMSHC_ENHANCED_STROBE;
++ else
++ vendor &= ~DWCMSHC_ENHANCED_STROBE;
++ sdhci_writel(host, vendor, reg);
++
++ return 0;
++}
++
+ static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
+ {
+ struct mmc *mmc = host->mmc;
+@@ -519,6 +560,7 @@ static const struct sdhci_data rk3568_data = {
+ .get_phy = rk3568_emmc_get_phy,
+ .emmc_phy_init = rk3568_emmc_phy_init,
+ .set_ios_post = rk3568_sdhci_set_ios_post,
++ .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
+ };
+
+ static const struct udevice_id sdhci_ids[] = {
diff --git a/PKGBUILD b/PKGBUILD
index 11fa34c..b30f250 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -6,9 +6,8 @@
pkgname=uboot-pinephonepro
pkgver=2022.01
-pkgrel=1
+pkgrel=0.1
epoch=4
-_srcname=u-boot-pine64-pinephonepro
_tfaver=2.6
pkgdesc="U-Boot for Pine64 PinePhone Pro"
arch=('aarch64')
@@ -20,14 +19,20 @@ provides=('uboot')
conflicts=('uboot')
install=${pkgname}.install
source=("ftp://ftp.denx.de/pub/u-boot/u-boot-${pkgver/rc/-rc}.tar.bz2"
- "https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/snapshot/trusted-firmware-a-$_tfaver.tar.gz"
+ "https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/snapshot/trusted-firmware-a-${_tfaver}.tar.gz"
"boot.txt"
"ppp-prepare-fstab"
"ppp-prepare-fstab.service"
"ppp-uboot-flash"
"ppp-uboot-mkscr"
- "0001-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch"
- "0002-Correct-boot-order-to-be-USB-SD-eMMC.patch")
+ "1001-Correct-boot-order-to-be-USB-SD-eMMC.patch"
+ "1002-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch"
+ #"1003-Configure-USB-power-settings-for-PinePhone-Pro.patch"
+ "2001-phy-Track-power-on-and-init-counts-in-uclass.patch"
+ "2002-mmc-sdhci-Add-HS400-Enhanced-Strobe-support.patch"
+ "2003-rockchip-sdhci-Fix-RK3399-eMMC-PHY-power-cycling.patch"
+ "2004-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3399.patch"
+ "2005-rockchip-sdhci-Add-HS400-Enhanced-Strobe-support-for-RK3568.patch")
sha256sums=('81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413'
'4e59f02ccb042d5d18c89c849701b96e6cf4b788709564405354b5d313d173f7'
'4e356b3868c0c1ac061c2c15c7ba80c627e1743214680409f418f9b4c00eb3f7'
@@ -35,19 +40,37 @@ sha256sums=('81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413'
'e55fb02dfb6213eabbb899b468dc5f68d36a11c05feda4c14e80282415222fea'
'6265fb9d3bc84bf1217383b52587b1d5a36372d88a824932586a802a502f62ba'
'05eaccb2e8ea1eba3e86a4e7fcf12fd232195b5018c049ddf36e5a82a968cc24'
+ '017d33aac55f8a5ed22170c97b4792ba755a4dad04f6c0cdd85119bbc81e87b3'
'7c3d76f4bee0e54900142043241248072e334387065212141e1f600afe0aafba'
- '017d33aac55f8a5ed22170c97b4792ba755a4dad04f6c0cdd85119bbc81e87b3')
+ #'b750ba47843defafd8be1cc2615983c93e9cde5a4f5a7b55308a6f00f3fe6611'
+ 'feb6ed9924f1b8f76066002cf3e414592e9ac8977f8e7aca8adc0c3d8bdb687f'
+ '68ff1130b396cf106ee16fd2e697fc61eb6fb3e873d78551b8247de73386ed1e'
+ 'ee52b4374f159e648b6b21e40b399804c763bb3ddde60b016fcd6e0da8135f2f'
+ '17e4adb43ac13a1297b5df8e1b7d3d03b555f5b5bc2085647e105cbd0897a238'
+ 'dd87bb8f7f5f7bdfdb3294b371c9aae2ab395c395ba1875f5772d0533c60b07f')
prepare() {
+ apply_patches() {
+ local PATCH
+ for PATCH in "${source[@]}"; do
+ PATCH="${PATCH%%::*}"
+ PATCH="${PATCH##*/}"
+ [[ ${PATCH} = $1*.patch ]] || continue
+ msg2 "Applying patch: ${PATCH}..."
+ patch -N -p1 < "../${PATCH}"
+ done
+ }
+
cd u-boot-${pkgver/rc/-rc}
- local src
- for src in "${source[@]}"; do
- src="${src%%::*}"
- src="${src##*/}"
- [[ $src = *.patch ]] || continue
- msg2 "Applying patch: $src..."
- patch -Np1 < "../$src"
- done
+
+ # Patches specific to the PinePhone Pro
+ # NOTE: Patch "1003-Configure-USB-power-settings-for-PinePhone-Pro.patch"
+ # is disabled temporarily because it's currently not in usable state, but
+ # it will be reworked in the next few days
+ apply_patches 1
+
+ # Patches from the U-Boot repository or mailing list
+ apply_patches 2
}
build() {
@@ -67,11 +90,11 @@ build() {
unset CFLAGS CXXFLAGS CPPFLAGS LDFLAGS
- cd trusted-firmware-a-$_tfaver
+ cd trusted-firmware-a-${_tfaver}
echo -e "\nBuilding TF-A for Pine64 PinePhone Pro...\n"
make PLAT=rk3399
- cp build/rk3399/release/bl31/bl31.elf ../u-boot-${_commit}
+ cp build/rk3399/release/bl31/bl31.elf ../u-boot-${pkgver/rc/-rc}
cd ../u-boot-${pkgver/rc/-rc}
@@ -80,12 +103,6 @@ build() {
update_config 'CONFIG_IDENT_STRING' '" Manjaro Linux ARM"'
update_config 'CONFIG_BOOTDELAY' '0'
- update_config 'CONFIG_USB_EHCI_HCD' 'n'
- update_config 'CONFIG_USB_EHCI_GENERIC' 'n'
- update_config 'CONFIG_USB_XHCI_HCD' 'n'
- update_config 'CONFIG_USB_XHCI_DWC3' 'n'
- update_config 'CONFIG_USB_DWC3' 'n'
- update_config 'CONFIG_USB_DWC3_GENERIC' 'n'
make EXTRAVERSION=-${pkgrel}
}
--
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