From dc506f0c945e15b655e523948688d5a11d80bc5e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Philip=20M=C3=BCller?= <philm@manjaro.org>
Date: Fri, 21 Jan 2022 23:26:14 +0100
Subject: [PATCH] [pkg-upd] 2022.01-0
---
...nd-add-HS400-Enhanced-Strobe-support.patch | 959 ++++++++++++++++++
PKGBUILD | 20 +-
2 files changed, 970 insertions(+), 9 deletions(-)
create mode 100644 0004-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch
diff --git a/0004-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch b/0004-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch
new file mode 100644
index 0000000..fdd0a71
--- /dev/null
+++ b/0004-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch
@@ -0,0 +1,959 @@
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+ Sun, 16 Jan 2022 12:18:31 -0800 (PST)
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Cc: Aswath Govindraju <a-govindraju@ti.com>,
+ Kever Yang <kever.yang@rock-chips.com>,
+ Philipp Tomsich <philipp.tomsich@vrull.eu>,
+ Samuel Dionne-Riel <samuel@dionne-riel.com>,
+ Stephen Carlson <stcarlso@linux.microsoft.com>,
+ Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
+ Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
+ Jaehoon Chung <jh80.chung@samsung.com>,
+ Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>,
+ Michal Simek <michal.simek@xilinx.com>, Peng Fan <peng.fan@nxp.com>,
+ Yifeng Zhao <yifeng.zhao@rock-chips.com>,
+ Jagan Teki <jagan@amarulasolutions.com>,
+ Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Subject: [PATCH v3 1/4] mmc: sdhci: Add HS400 Enhanced Strobe support
+Date: Sun, 16 Jan 2022 23:18:10 +0300
+Message-Id: <20220116201814.11672-2-alpernebiyasak@gmail.com>
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+
+Delegate setting the Enhanced Strobe configuration to individual drivers
+if they set a function for it. Return -ENOTSUPP if they do not, like
+what the MMC uclass does.
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
+---
+
+(no changes since v2)
+
+Changes in v2:
+- Add tag: "Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>"
+
+ drivers/mmc/sdhci.c | 18 ++++++++++++++++++
+ include/sdhci.h | 1 +
+ 2 files changed, 19 insertions(+)
+
+diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
+index 766e4a6b0c5e..bf989a594f7e 100644
+--- a/drivers/mmc/sdhci.c
++++ b/drivers/mmc/sdhci.c
+@@ -513,6 +513,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
+ reg |= SDHCI_CTRL_UHS_SDR104;
+ break;
+ case MMC_HS_400:
++ case MMC_HS_400_ES:
+ reg |= SDHCI_CTRL_HS400;
+ break;
+ default:
+@@ -666,6 +667,7 @@ static int sdhci_set_ios(struct mmc *mmc)
+ mmc->selected_mode == MMC_DDR_52 ||
+ mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400 ||
++ mmc->selected_mode == MMC_HS_400_ES ||
+ mmc->selected_mode == UHS_SDR25 ||
+ mmc->selected_mode == UHS_SDR50 ||
+ mmc->selected_mode == UHS_SDR104 ||
+@@ -799,6 +801,19 @@ static int sdhci_wait_dat0(struct udevice *dev, int state,
+ return -ETIMEDOUT;
+ }
+
++#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
++static int sdhci_set_enhanced_strobe(struct udevice *dev)
++{
++ struct mmc *mmc = mmc_get_mmc_dev(dev);
++ struct sdhci_host *host = mmc->priv;
++
++ if (host->ops && host->ops->set_enhanced_strobe)
++ return host->ops->set_enhanced_strobe(host);
++
++ return -ENOTSUPP;
++}
++#endif
++
+ const struct dm_mmc_ops sdhci_ops = {
+ .send_cmd = sdhci_send_command,
+ .set_ios = sdhci_set_ios,
+@@ -808,6 +823,9 @@ const struct dm_mmc_ops sdhci_ops = {
+ .execute_tuning = sdhci_execute_tuning,
+ #endif
+ .wait_dat0 = sdhci_wait_dat0,
++#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
++ .set_enhanced_strobe = sdhci_set_enhanced_strobe,
++#endif
+ };
+ #else
+ static const struct mmc_ops sdhci_ops = {
+diff --git a/include/sdhci.h b/include/sdhci.h
+index c718dd7206c1..7a65fdf95d30 100644
+--- a/include/sdhci.h
++++ b/include/sdhci.h
+@@ -272,6 +272,7 @@ struct sdhci_ops {
+ int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+ int (*set_delay)(struct sdhci_host *host);
+ int (*deferred_probe)(struct sdhci_host *host);
++ int (*set_enhanced_strobe)(struct sdhci_host *host);
+ };
+
+ #define ADMA_MAX_LEN 65532
+
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+ Sun, 16 Jan 2022 12:18:35 -0800 (PST)
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Cc: Aswath Govindraju <a-govindraju@ti.com>,
+ Kever Yang <kever.yang@rock-chips.com>,
+ Philipp Tomsich <philipp.tomsich@vrull.eu>,
+ Samuel Dionne-Riel <samuel@dionne-riel.com>,
+ Stephen Carlson <stcarlso@linux.microsoft.com>,
+ Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
+ Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
+ Jaehoon Chung <jh80.chung@samsung.com>,
+ Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>,
+ Michal Simek <michal.simek@xilinx.com>, Peng Fan <peng.fan@nxp.com>,
+ Yifeng Zhao <yifeng.zhao@rock-chips.com>,
+ Jagan Teki <jagan@amarulasolutions.com>,
+ Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Subject: [PATCH v3 2/4] rockchip: sdhci: Fix RK3399 eMMC PHY power cycling
+Date: Sun, 16 Jan 2022 23:18:11 +0300
+Message-Id: <20220116201814.11672-3-alpernebiyasak@gmail.com>
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+
+The Rockchip RK3399 eMMC PHY has to be power-cycled while changing its
+clock speed to some higher speeds. This is dependent on the desired
+SDHCI clock speed, and it looks like the PHY should be powered off while
+setting the SDHCI clock in these cases.
+
+Commit ac804143cfd1 ("mmc: rockchip_sdhci: add phy and clock config for
+rk3399") attempts to do this in the set_ios_post() hook by setting the
+SDHCI clock once more while the PHY is turned off/on as necessary, as
+the SDHCI framework does not provide a way to override how it sets its
+clock. However, the commit breaks reinitializing the eMMC on a few
+boards including chromebook_kevin and reportedly ROCKPro64.
+
+This patch reworks the power cycling to utilize the SDHCI framework
+slightly better (using the set_control_reg() hook to power off the PHY
+and set_ios_post() hook to power it back on) which happens to fix the
+issue, at least on a chromebook_kevin.
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+---
+RK3568 parts only build-tested as I don't have a RK3568 board.
+
+(no changes since v2)
+
+Changes in v2:
+- Add this patch
+
+ drivers/mmc/rockchip_sdhci.c | 53 +++++++++++++++++++++++++++++-------
+ 1 file changed, 43 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
+index 278473899c7c..f0d7ba4774d6 100644
+--- a/drivers/mmc/rockchip_sdhci.c
++++ b/drivers/mmc/rockchip_sdhci.c
+@@ -90,9 +90,10 @@ struct rockchip_sdhc {
+ };
+
+ struct sdhci_data {
+- int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
+ int (*emmc_phy_init)(struct udevice *dev);
+ int (*get_phy)(struct udevice *dev);
++ void (*set_control_reg)(struct sdhci_host *host);
++ int (*set_ios_post)(struct sdhci_host *host);
+ };
+
+ static int rk3399_emmc_phy_init(struct udevice *dev)
+@@ -182,15 +183,28 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
+-static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
++static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
+ {
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct mmc *mmc = host->mmc;
++ uint clock = mmc->tran_speed;
+ int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
+
+ if (cycle_phy)
+ rk3399_emmc_phy_power_off(priv->phy);
+
+- sdhci_set_clock(host->mmc, clock);
++ sdhci_set_control_reg(host);
++};
++
++static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct mmc *mmc = host->mmc;
++ uint clock = mmc->tran_speed;
++ int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
++
++ if (!clock)
++ clock = mmc->clock;
+
+ if (cycle_phy)
+ rk3399_emmc_phy_power_on(priv->phy, clock);
+@@ -269,10 +283,8 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
+-static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
++static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
+ {
+- struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+- struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+ struct mmc *mmc = host->mmc;
+ uint clock = mmc->tran_speed;
+ u32 reg;
+@@ -280,8 +292,7 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
+ if (!clock)
+ clock = mmc->clock;
+
+- if (data->emmc_set_clock)
+- data->emmc_set_clock(host, clock);
++ rk3568_sdhci_emmc_set_clock(host, clock);
+
+ if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+@@ -295,6 +306,26 @@ static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
+ return 0;
+ }
+
++static void rockchip_sdhci_set_control_reg(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
++
++ if (data->set_control_reg)
++ data->set_control_reg(host);
++}
++
++static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
++
++ if (data->set_ios_post)
++ return data->set_ios_post(host);
++
++ return 0;
++}
++
+ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+ {
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+@@ -358,6 +389,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+ static struct sdhci_ops rockchip_sdhci_ops = {
+ .set_ios_post = rockchip_sdhci_set_ios_post,
+ .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
++ .set_control_reg = rockchip_sdhci_set_control_reg,
+ };
+
+ static int rockchip_sdhci_probe(struct udevice *dev)
+@@ -436,15 +468,16 @@ static int rockchip_sdhci_bind(struct udevice *dev)
+ }
+
+ static const struct sdhci_data rk3399_data = {
+- .emmc_set_clock = rk3399_sdhci_emmc_set_clock,
+ .get_phy = rk3399_emmc_get_phy,
+ .emmc_phy_init = rk3399_emmc_phy_init,
++ .set_control_reg = rk3399_sdhci_set_control_reg,
++ .set_ios_post = rk3399_sdhci_set_ios_post,
+ };
+
+ static const struct sdhci_data rk3568_data = {
+- .emmc_set_clock = rk3568_sdhci_emmc_set_clock,
+ .get_phy = rk3568_emmc_get_phy,
+ .emmc_phy_init = rk3568_emmc_phy_init,
++ .set_ios_post = rk3568_sdhci_set_ios_post,
+ };
+
+ static const struct udevice_id sdhci_ids[] = {
+
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+ Sun, 16 Jan 2022 12:18:39 -0800 (PST)
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Cc: Aswath Govindraju <a-govindraju@ti.com>,
+ Kever Yang <kever.yang@rock-chips.com>,
+ Philipp Tomsich <philipp.tomsich@vrull.eu>,
+ Samuel Dionne-Riel <samuel@dionne-riel.com>,
+ Stephen Carlson <stcarlso@linux.microsoft.com>,
+ Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
+ Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
+ Jaehoon Chung <jh80.chung@samsung.com>,
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+ Michal Simek <michal.simek@xilinx.com>, Peng Fan <peng.fan@nxp.com>,
+ Yifeng Zhao <yifeng.zhao@rock-chips.com>,
+ Jagan Teki <jagan@amarulasolutions.com>,
+ Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Subject: [PATCH v3 3/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for
+ RK3399
+Date: Sun, 16 Jan 2022 23:18:12 +0300
+Message-Id: <20220116201814.11672-4-alpernebiyasak@gmail.com>
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+
+On RK3399, a register bit must be set to enable Enhanced Strobe.
+Let the Rockchip SDHCI driver set it when Enhanced Strobe configuration
+is requested. However, having it set makes the lower-speed modes stop
+working and makes reinitialization fail, so let it be unset as needed in
+set_control_reg().
+
+This is mostly ported from Linux's Arasan SDHCI driver which happens
+to be the underlying IP. (drivers/mmc/host/sdhci-of-arasan.c in Linux
+tree).
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+---
+
+(no changes since v2)
+
+Changes in v2:
+- Unset ES bit in rk3399 set_control_reg() to fix a reinit issue
+- Don't use unnecessary & for function pointer in ops struct
+- Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe
+- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
+
+ drivers/mmc/rockchip_sdhci.c | 41 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
+index f0d7ba4774d6..f920c5141142 100644
+--- a/drivers/mmc/rockchip_sdhci.c
++++ b/drivers/mmc/rockchip_sdhci.c
+@@ -42,6 +42,9 @@
+ ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
+ PHYCTRL_DLLRDY_DONE)
+
++#define ARASAN_VENDOR_REGISTER 0x78
++#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
++
+ /* Rockchip specific Registers */
+ #define DWCMSHC_EMMC_DLL_CTRL 0x800
+ #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
+@@ -94,6 +97,7 @@ struct sdhci_data {
+ int (*get_phy)(struct udevice *dev);
+ void (*set_control_reg)(struct sdhci_host *host);
+ int (*set_ios_post)(struct sdhci_host *host);
++ int (*set_enhanced_strobe)(struct sdhci_host *host);
+ };
+
+ static int rk3399_emmc_phy_init(struct udevice *dev)
+@@ -183,6 +187,21 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
++static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
++{
++ struct mmc *mmc = host->mmc;
++ u32 vendor;
++
++ vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
++ if (mmc->selected_mode == MMC_HS_400_ES)
++ vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
++ else
++ vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
++ sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
++
++ return 0;
++}
++
+ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
+ {
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+@@ -194,6 +213,15 @@ static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
+ rk3399_emmc_phy_power_off(priv->phy);
+
+ sdhci_set_control_reg(host);
++
++ /*
++ * Reinitializing the device tries to set it to lower-speed modes
++ * first, which fails if the Enhanced Strobe bit is set, making
++ * the device impossible to use. Set the correct value here to
++ * let reinitialization attempts succeed.
++ */
++ if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
++ rk3399_sdhci_set_enhanced_strobe(host);
+ };
+
+ static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
+@@ -386,10 +414,22 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+ return ret;
+ }
+
++static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
++{
++ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
++ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
++
++ if (data->set_enhanced_strobe)
++ return data->set_enhanced_strobe(host);
++
++ return -ENOTSUPP;
++}
++
+ static struct sdhci_ops rockchip_sdhci_ops = {
+ .set_ios_post = rockchip_sdhci_set_ios_post,
+ .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
+ .set_control_reg = rockchip_sdhci_set_control_reg,
++ .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
+ };
+
+ static int rockchip_sdhci_probe(struct udevice *dev)
+@@ -472,6 +512,7 @@ static const struct sdhci_data rk3399_data = {
+ .emmc_phy_init = rk3399_emmc_phy_init,
+ .set_control_reg = rk3399_sdhci_set_control_reg,
+ .set_ios_post = rk3399_sdhci_set_ios_post,
++ .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
+ };
+
+ static const struct sdhci_data rk3568_data = {
+
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+ Sun, 16 Jan 2022 12:18:44 -0800 (PST)
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+To: u-boot@lists.denx.de
+Cc: Aswath Govindraju <a-govindraju@ti.com>,
+ Kever Yang <kever.yang@rock-chips.com>,
+ Philipp Tomsich <philipp.tomsich@vrull.eu>,
+ Samuel Dionne-Riel <samuel@dionne-riel.com>,
+ Stephen Carlson <stcarlso@linux.microsoft.com>,
+ Peter Robinson <pbrobinson@gmail.com>, Faiz Abbas <faiz_abbas@ti.com>,
+ Jack Mitchell <ml@embed.me.uk>, Simon Glass <sjg@chromium.org>,
+ Jaehoon Chung <jh80.chung@samsung.com>,
+ Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>,
+ Michal Simek <michal.simek@xilinx.com>, Peng Fan <peng.fan@nxp.com>,
+ Yifeng Zhao <yifeng.zhao@rock-chips.com>,
+ Jagan Teki <jagan@amarulasolutions.com>,
+ Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Subject: [PATCH v3 4/4] rockchip: sdhci: Add HS400 Enhanced Strobe support for
+ RK3568
+Date: Sun, 16 Jan 2022 23:18:13 +0300
+Message-Id: <20220116201814.11672-5-alpernebiyasak@gmail.com>
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+
+On RK3568, a register bit must be set to enable Enhanced Strobe.
+However, it appears that the address of this register may differ from
+vendor to vendor and should be read from the underlying MMC IP. Let the
+Rockchip SDHCI driver read this address and set the relevant bit when
+Enhanced Strobe configuration is requested.
+
+Additionally, a bit signifying that the connected hardware is an eMMC
+chip must be set to enable Data Strobe for HS400 and HS400ES modes. Also
+make the driver set this bit as appropriate.
+
+This is partly ported from Linux's Synopsys DWC MSHC driver which
+happens to be the underlying IP. (drivers/mmc/host/sdhci-of-dwcmshc.c in
+Linux tree).
+
+Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+---
+Only build-tested as I don't have a RK3568 board.
+
+Changes in v3:
+- Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init()
+
+Changes in v2:
+- Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe
+- Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES
+
+ drivers/mmc/rockchip_sdhci.c | 42 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
+index f920c5141142..4c7cc7535e2e 100644
+--- a/drivers/mmc/rockchip_sdhci.c
++++ b/drivers/mmc/rockchip_sdhci.c
+@@ -45,6 +45,14 @@
+ #define ARASAN_VENDOR_REGISTER 0x78
+ #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
+
++/* DWC IP vendor area 1 pointer */
++#define DWCMSHC_P_VENDOR_AREA1 0xe8
++#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
++/* Offset inside the vendor area 1 */
++#define DWCMSHC_EMMC_CONTROL 0x2c
++#define DWCMSHC_CARD_IS_EMMC BIT(0)
++#define DWCMSHC_ENHANCED_STROBE BIT(8)
++
+ /* Rockchip specific Registers */
+ #define DWCMSHC_EMMC_DLL_CTRL 0x800
+ #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
+@@ -244,11 +252,25 @@ static int rk3568_emmc_phy_init(struct udevice *dev)
+ {
+ struct rockchip_sdhc *prv = dev_get_priv(dev);
+ struct sdhci_host *host = &prv->host;
++ struct mmc *mmc = host->mmc;
+ u32 extra;
++ u32 vendor;
++ int reg;
+
+ extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+
++ /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 and HS400ES */
++ reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
++ + DWCMSHC_EMMC_CONTROL;
++
++ vendor = sdhci_readw(host, reg);
++ if (IS_MMC(mmc))
++ vendor |= DWCMSHC_CARD_IS_EMMC;
++ else
++ vendor &= ~DWCMSHC_CARD_IS_EMMC;
++ sdhci_writew(host, vendor, reg);
++
+ return 0;
+ }
+
+@@ -311,6 +333,25 @@ static int rk3568_emmc_get_phy(struct udevice *dev)
+ return 0;
+ }
+
++static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
++{
++ struct mmc *mmc = host->mmc;
++ u32 vendor;
++ int reg;
++
++ reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
++ + DWCMSHC_EMMC_CONTROL;
++
++ vendor = sdhci_readl(host, reg);
++ if (mmc->selected_mode == MMC_HS_400_ES)
++ vendor |= DWCMSHC_ENHANCED_STROBE;
++ else
++ vendor &= ~DWCMSHC_ENHANCED_STROBE;
++ sdhci_writel(host, vendor, reg);
++
++ return 0;
++}
++
+ static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
+ {
+ struct mmc *mmc = host->mmc;
+@@ -519,6 +560,7 @@ static const struct sdhci_data rk3568_data = {
+ .get_phy = rk3568_emmc_get_phy,
+ .emmc_phy_init = rk3568_emmc_phy_init,
+ .set_ios_post = rk3568_sdhci_set_ios_post,
++ .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
+ };
+
+ static const struct udevice_id sdhci_ids[] = {
diff --git a/PKGBUILD b/PKGBUILD
index 5def72b..a9b3bf5 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -1,4 +1,5 @@
# U-Boot: Pinephone Pro based on PKGBUILD for RK3399
+# Maintainer: Philip Müller <philm@manjaro.org>
# Contributor: Furkan Kardame <furkan@fkardame.com>
# Contributor: Dan Johansen <strit@manjaro.org>
# Contributor: Dragan Simic <dsimic@buserror.io>
@@ -6,9 +7,8 @@
pkgname=uboot-pinephonepro
pkgver=2022.01
pkgrel=0
-epoch=1
+epoch=3
_srcname=u-boot-pine64-pinephonepro
-_commit=d637294e264adfeb29f390dfc393106fd4d41b17
_tfaver=2.6
pkgdesc="U-Boot for Pine64 PinePhone Pro"
arch=('aarch64')
@@ -19,7 +19,7 @@ depends=('uboot-tools')
provides=('uboot')
conflicts=('uboot')
install=${pkgname}.install
-source=("u-boot-$_commit.tar.gz::https://source.denx.de/u-boot/u-boot/-/archive/${_commit}/u-boot-${_commit}.tar.gz"
+source=("ftp://ftp.denx.de/pub/u-boot/u-boot-${pkgver/rc/-rc}.tar.bz2"
"https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/snapshot/trusted-firmware-a-$_tfaver.tar.gz"
"boot.txt"
"ppp-prepare-fstab"
@@ -28,8 +28,9 @@ source=("u-boot-$_commit.tar.gz::https://source.denx.de/u-boot/u-boot/-/archive/
"ppp-uboot-mkscr"
"0001-rockchip-Add-initial-support-for-the-PinePhone-Pro.patch"
"0002-Correct-boot-order-to-be-USB-SD-eMMC.patch"
- "0003-Configure-USB-power-settings-for-PinePhone-Pro.patch")
-sha256sums=('d69b85ee6a153cd79e17085421c5f20c8d3037c57abe84f87d8402ce9d9b3131'
+ "0003-Configure-USB-power-settings-for-PinePhone-Pro.patch"
+ "0004-rockchip-sdhci-Fix-reinit-and-add-HS400-Enhanced-Strobe-support.patch")
+sha256sums=('81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413'
'4e59f02ccb042d5d18c89c849701b96e6cf4b788709564405354b5d313d173f7'
'4e356b3868c0c1ac061c2c15c7ba80c627e1743214680409f418f9b4c00eb3f7'
'de7e36cdc7ed2fb5abb9155c97f87926361aa5be87d794c9016776160f3430ec'
@@ -38,10 +39,11 @@ sha256sums=('d69b85ee6a153cd79e17085421c5f20c8d3037c57abe84f87d8402ce9d9b3131'
'05eaccb2e8ea1eba3e86a4e7fcf12fd232195b5018c049ddf36e5a82a968cc24'
'7c3d76f4bee0e54900142043241248072e334387065212141e1f600afe0aafba'
'017d33aac55f8a5ed22170c97b4792ba755a4dad04f6c0cdd85119bbc81e87b3'
- 'b750ba47843defafd8be1cc2615983c93e9cde5a4f5a7b55308a6f00f3fe6611')
+ 'b750ba47843defafd8be1cc2615983c93e9cde5a4f5a7b55308a6f00f3fe6611'
+ 'eceafbaca3fc92e406bd5ff5e3cdf7f46b9be2426f94ce38eb5e5ce07f43f3b4')
prepare() {
- cd u-boot-${_commit}
+ cd u-boot-${pkgver/rc/-rc}
local src
for src in "${source[@]}"; do
src="${src%%::*}"
@@ -75,7 +77,7 @@ build() {
make PLAT=rk3399
cp build/rk3399/release/bl31/bl31.elf ../u-boot-${_commit}
- cd ../u-boot-${_commit}
+ cd ../u-boot-${pkgver/rc/-rc}
echo -e "\nBuilding U-Boot for Pine64 PinePhone Pro...\n"
make pinephone-pro-rk3399_defconfig
@@ -93,7 +95,7 @@ build() {
}
package() {
- cd u-boot-${_commit}
+ cd u-boot-${pkgver/rc/-rc}
install -D -m 0644 idbloader.img u-boot.itb -t "${pkgdir}/boot"
install -D -m 0644 "${srcdir}/boot.txt" -t "${pkgdir}/boot"
--
GitLab