diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c078849df7f9712349e0e5c1f721d977953f8e3f..f66294b4f9d29d31fbec1075aabf3483be352309 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -348,7 +348,7 @@ config MEM_MT48LC16M16A2TG_75
config MEM_MT48LC32M8A2_75
bool
- depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
+ depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
default y
config MEM_MT48LC8M32B2B5_7
@@ -361,11 +361,6 @@ config MEM_MT48LC32M16A2TG_75
depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
default y
-config MEM_MT48LC32M8A2_75
- bool
- depends on (BFIN518F_EZBRD)
- default y
-
config MEM_MT48H32M16LFCJ_75
bool
depends on (BFIN526_EZBRD)
@@ -791,6 +786,34 @@ config MEMCPY_L1
If enabled, the memcpy function is linked
into L1 instruction memory. (less latency)
+config STRCMP_L1
+ bool "locate strcmp function in L1 Memory"
+ default y
+ help
+ If enabled, the strcmp function is linked
+ into L1 instruction memory (less latency).
+
+config STRNCMP_L1
+ bool "locate strncmp function in L1 Memory"
+ default y
+ help
+ If enabled, the strncmp function is linked
+ into L1 instruction memory (less latency).
+
+config STRCPY_L1
+ bool "locate strcpy function in L1 Memory"
+ default y
+ help
+ If enabled, the strcpy function is linked
+ into L1 instruction memory (less latency).
+
+config STRNCPY_L1
+ bool "locate strncpy function in L1 Memory"
+ default y
+ help
+ If enabled, the strncpy function is linked
+ into L1 instruction memory (less latency).
+
config SYS_BFIN_SPINLOCK_L1
bool "Locate sys_bfin_spinlock function in L1 Memory"
default y
@@ -1187,32 +1210,6 @@ config PM_BFIN_SLEEP
If unsure, select "Sleep Deeper".
endchoice
-config PM_WAKEUP_BY_GPIO
- bool "Allow Wakeup from Standby by GPIO"
- depends on PM && !BF54x
-
-config PM_WAKEUP_GPIO_NUMBER
- int "GPIO number"
- range 0 47
- depends on PM_WAKEUP_BY_GPIO
- default 2
-
-choice
- prompt "GPIO Polarity"
- depends on PM_WAKEUP_BY_GPIO
- default PM_WAKEUP_GPIO_POLAR_H
-config PM_WAKEUP_GPIO_POLAR_H
- bool "Active High"
-config PM_WAKEUP_GPIO_POLAR_L
- bool "Active Low"
-config PM_WAKEUP_GPIO_POLAR_EDGE_F
- bool "Falling EDGE"
-config PM_WAKEUP_GPIO_POLAR_EDGE_R
- bool "Rising EDGE"
-config PM_WAKEUP_GPIO_POLAR_EDGE_B
- bool "Both EDGE"
-endchoice
-
comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
depends on PM
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index aec89a5280b2249ef8890c14ddd96918de36838b..d1825cb247685dacb6175f58829bec48edb6c03f 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -238,7 +238,7 @@ config EARLY_PRINTK
config NMI_WATCHDOG
bool "Enable NMI watchdog to help debugging lockup on SMP"
default n
- depends on (SMP && !BFIN_SCRATCH_REG_RETN)
+ depends on SMP
help
If any CPU in the system does not execute the period local timer
interrupt for more than 5 seconds, then the NMI handler dumps debug
@@ -264,4 +264,13 @@ config BFIN_ISRAM_SELF_TEST
help
Run some self tests of the isram driver code at boot.
+config BFIN_PSEUDODBG_INSNS
+ bool "Support pseudo debug instructions"
+ default n
+ help
+ This option allows the kernel to emulate some pseudo instructions which
+ allow simulator test cases to be run under Linux with no changes.
+
+ Most people should say N here.
+
endmenu
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index e6485c305ea6e53266412712216136ec126cac4b..121cc04d877d891c1e4594a9ade1795abf5991e4 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -39,9 +39,15 @@ extern unsigned long sclk_to_usecs(unsigned long sclk);
extern unsigned long usecs_to_sclk(unsigned long usecs);
struct pt_regs;
+#if defined(CONFIG_DEBUG_VERBOSE)
extern void dump_bfin_process(struct pt_regs *regs);
extern void dump_bfin_mem(struct pt_regs *regs);
extern void dump_bfin_trace_buffer(void);
+#else
+#define dump_bfin_process(regs)
+#define dump_bfin_mem(regs)
+#define dump_bfin_trace_buffer()
+#endif
/* init functions only */
extern int init_arch_irq(void);
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
index 75f6dc336d46d4b13e04a42bf8facb44ea79a49f..8d9b1eba89c48ad57a1437c0e19716082266cc69 100644
--- a/arch/blackfin/include/asm/bug.h
+++ b/arch/blackfin/include/asm/bug.h
@@ -9,7 +9,12 @@
#ifdef CONFIG_BUG
-#define BFIN_BUG_OPCODE 0xefcd
+/*
+ * This can be any undefined 16-bit opcode, meaning
+ * ((opcode & 0xc000) != 0xc000)
+ * Anything from 0x0001 to 0x000A (inclusive) will work
+ */
+#define BFIN_BUG_OPCODE 0x0001
#ifdef CONFIG_DEBUG_BUGVERBOSE
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 8542bc31f63cae7445482a4a46b41d797f06acfd..93f6c634fdf4cbfdb5399e6327baef82096cf390 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -15,6 +15,8 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES L1_CACHE_BYTES
+#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
+
#ifdef CONFIG_SMP
#define __cacheline_aligned
#else
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 91bd2d7b9d5541fdb56271e94f1d9dcd68054be8..01b19d0cf50974be13f804e6175f9f814d1e136b 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -167,23 +167,23 @@ int bfin_special_gpio_request(unsigned gpio, const char *label);
#endif
#ifdef CONFIG_PM
+int bfin_pm_standby_ctrl(unsigned ctrl);
-unsigned int bfin_pm_standby_setup(void);
-void bfin_pm_standby_restore(void);
+static inline int bfin_pm_standby_setup(void)
+{
+ return bfin_pm_standby_ctrl(1);
+}
+
+static inline void bfin_pm_standby_restore(void)
+{
+ bfin_pm_standby_ctrl(0);
+}
void bfin_gpio_pm_hibernate_restore(void);
void bfin_gpio_pm_hibernate_suspend(void);
#ifndef CONFIG_BF54x
-#define PM_WAKE_RISING 0x1
-#define PM_WAKE_FALLING 0x2
-#define PM_WAKE_HIGH 0x4
-#define PM_WAKE_LOW 0x8
-#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
-#define PM_WAKE_IGNORE 0xF0
-
-int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
-void gpio_pm_wakeup_free(unsigned gpio);
+int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
struct gpio_port_s {
unsigned short data;
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
index 821c699c22387c2a607170a128cb2a962866360a..dcca3e6d6e808b1423654315912de2f00eedab2e 100644
--- a/arch/blackfin/include/asm/pgtable.h
+++ b/arch/blackfin/include/asm/pgtable.h
@@ -80,7 +80,8 @@ PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
*/
-#define ZERO_PAGE(vaddr) (virt_to_page(0))
+#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
+extern char empty_zero_page[];
extern unsigned int kobjsize(const void *objp);
diff --git a/arch/blackfin/include/asm/pseudo_instructions.h b/arch/blackfin/include/asm/pseudo_instructions.h
new file mode 100644
index 0000000000000000000000000000000000000000..b00adfa08169ab5ab5e59efdd728a2b7810b953a
--- /dev/null
+++ b/arch/blackfin/include/asm/pseudo_instructions.h
@@ -0,0 +1,18 @@
+/*
+ * header file for pseudo instructions
+ *
+ * Copyright 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BLACKFIN_PSEUDO_
+#define _BLACKFIN_PSEUDO_
+
+#include <linux/types.h>
+#include <asm/ptrace.h>
+
+extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode);
+extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode);
+
+#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
index d7f0ccb418c347e5d9bb7e15f2c0a131d9c1d5b7..423c099aa988f6749e7c4a55479c4141b52ef818 100644
--- a/arch/blackfin/include/asm/string.h
+++ b/arch/blackfin/include/asm/string.h
@@ -12,121 +12,16 @@
#ifdef __KERNEL__ /* only set these up for kernel code */
#define __HAVE_ARCH_STRCPY
-extern inline char *strcpy(char *dest, const char *src)
-{
- char *xdest = dest;
- char temp = 0;
-
- __asm__ __volatile__ (
- "1:"
- "%2 = B [%1++] (Z);"
- "B [%0++] = %2;"
- "CC = %2;"
- "if cc jump 1b (bp);"
- : "+&a" (dest), "+&a" (src), "=&d" (temp)
- :
- : "memory", "CC");
-
- return xdest;
-}
+extern char *strcpy(char *dest, const char *src);
#define __HAVE_ARCH_STRNCPY
-extern inline char *strncpy(char *dest, const char *src, size_t n)
-{
- char *xdest = dest;
- char temp = 0;
-
- if (n == 0)
- return xdest;
-
- __asm__ __volatile__ (
- "1:"
- "%3 = B [%1++] (Z);"
- "B [%0++] = %3;"
- "CC = %3;"
- "if ! cc jump 2f;"
- "%2 += -1;"
- "CC = %2 == 0;"
- "if ! cc jump 1b (bp);"
- "jump 4f;"
- "2:"
- /* if src is shorter than n, we need to null pad bytes now */
- "%3 = 0;"
- "3:"
- "%2 += -1;"
- "CC = %2 == 0;"
- "if cc jump 4f;"
- "B [%0++] = %3;"
- "jump 3b;"
- "4:"
- : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
- :
- : "memory", "CC");
-
- return xdest;
-}
+extern char *strncpy(char *dest, const char *src, size_t n);
#define __HAVE_ARCH_STRCMP
-extern inline int strcmp(const char *cs, const char *ct)
-{
- /* need to use int's here so the char's in the assembly don't get
- * sign extended incorrectly when we don't want them to be
- */
- int __res1, __res2;
-
- __asm__ __volatile__ (
- "1:"
- "%2 = B[%0++] (Z);" /* get *cs */
- "%3 = B[%1++] (Z);" /* get *ct */
- "CC = %2 == %3;" /* compare a byte */
- "if ! cc jump 2f;" /* not equal, break out */
- "CC = %2;" /* at end of cs? */
- "if cc jump 1b (bp);" /* no, keep going */
- "jump.s 3f;" /* strings are equal */
- "2:"
- "%2 = %2 - %3;" /* *cs - *ct */
- "3:"
- : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
- :
- : "memory", "CC");
-
- return __res1;
-}
+extern int strcmp(const char *cs, const char *ct);
#define __HAVE_ARCH_STRNCMP
-extern inline int strncmp(const char *cs, const char *ct, size_t count)
-{
- /* need to use int's here so the char's in the assembly don't get
- * sign extended incorrectly when we don't want them to be
- */
- int __res1, __res2;
-
- if (!count)
- return 0;
-
- __asm__ __volatile__ (
- "1:"
- "%3 = B[%0++] (Z);" /* get *cs */
- "%4 = B[%1++] (Z);" /* get *ct */
- "CC = %3 == %4;" /* compare a byte */
- "if ! cc jump 3f;" /* not equal, break out */
- "CC = %3;" /* at end of cs? */
- "if ! cc jump 4f;" /* yes, all done */
- "%2 += -1;" /* no, adjust count */
- "CC = %2 == 0;"
- "if ! cc jump 1b;" /* more to do, keep going */
- "2:"
- "%3 = 0;" /* strings are equal */
- "jump.s 4f;"
- "3:"
- "%3 = %3 - %4;" /* *cs - *ct */
- "4:"
- : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
- :
- : "memory", "CC");
-
- return __res1;
-}
+extern int strncmp(const char *cs, const char *ct, size_t count);
#define __HAVE_ARCH_MEMSET
extern void *memset(void *s, int c, size_t count);
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h
index f1a06c006ed0260f91c32db07720a74d727a1c33..7c368682c0a3b13f7d85da165bc3aa7e0bc52ee1 100644
--- a/arch/blackfin/include/asm/tlbflush.h
+++ b/arch/blackfin/include/asm/tlbflush.h
@@ -1 +1,2 @@
#include <asm-generic/tlbflush.h>
+#define flush_tlb_kernel_range(s, e) do { } while (0)
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
index dc0aa55ae773420fb426733e0b437d089580a692..33589a29b8d87641b208dd6c7d3c7c7f129592f7 100644
--- a/arch/blackfin/include/asm/trace.h
+++ b/arch/blackfin/include/asm/trace.h
@@ -23,6 +23,13 @@
#ifndef __ASSEMBLY__
extern unsigned long trace_buff_offset;
extern unsigned long software_trace_buff[];
+#if defined(CONFIG_DEBUG_VERBOSE)
+extern void decode_address(char *buf, unsigned long address);
+extern bool get_instruction(unsigned int *val, unsigned short *address);
+#else
+static inline void decode_address(char *buf, unsigned long address) { }
+static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; }
+#endif
/* Trace Macros for C files */
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 346a421f1562fad53d66485d3d8d7ea2b51935ff..30d0d1f01dc7f0c017245ae75c5ba2693d335e87 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,8 @@ extra-y := init_task.o vmlinux.lds
obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
- fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o
+ fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o \
+ exception.o dumpstack.o
ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
obj-y += time-ts.o
@@ -29,6 +30,8 @@ obj-$(CONFIG_NMI_WATCHDOG) += nmi.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
+obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
+obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
# the kgdb test puts code into L2 and without linker
# relaxation, we need to force long calls to/from it
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index e35e20f00d9b3c864ec2a568afc86947f2a5681d..42833ee2b308ba546b323823a6bc2d37e94481ba 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -475,9 +475,7 @@ GET_GPIO_P(maskb)
#ifdef CONFIG_PM
-
static unsigned short wakeup_map[GPIO_BANK_NUM];
-static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
static const unsigned int sic_iwr_irqs[] = {
#if defined(BF533_FAMILY)
@@ -514,112 +512,26 @@ static const unsigned int sic_iwr_irqs[] = {
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
-int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
-{
- unsigned long flags;
-
- if ((check_gpio(gpio) < 0) || !type)
- return -EINVAL;
-
- local_irq_save_hw(flags);
- wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
- wakeup_flags_map[gpio] = type;
- local_irq_restore_hw(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(gpio_pm_wakeup_request);
-
-void gpio_pm_wakeup_free(unsigned gpio)
+int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
{
unsigned long flags;
if (check_gpio(gpio) < 0)
- return;
+ return -EINVAL;
local_irq_save_hw(flags);
-
- wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-
- local_irq_restore_hw(flags);
-}
-EXPORT_SYMBOL(gpio_pm_wakeup_free);
-
-static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
-{
- port_setup(gpio, GPIO_USAGE);
- set_gpio_dir(gpio, 0);
- set_gpio_inen(gpio, 1);
-
- if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
- set_gpio_edge(gpio, 1);
- else
- set_gpio_edge(gpio, 0);
-
- if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
- set_gpio_both(gpio, 1);
+ if (ctrl)
+ wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
else
- set_gpio_both(gpio, 0);
-
- if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
- set_gpio_polar(gpio, 1);
- else
- set_gpio_polar(gpio, 0);
+ wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- SSYNC();
-
- return 0;
-}
-
-u32 bfin_pm_standby_setup(void)
-{
- u16 bank, mask, i, gpio;
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- mask = wakeup_map[gpio_bank(i)];
- bank = gpio_bank(i);
-
- gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb;
- gpio_array[bank]->maskb = 0;
-
- if (mask) {
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].fer = *port_fer[bank];
-#endif
- gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
- gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
- gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
- gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
- gpio_bank_saved[bank].both = gpio_array[bank]->both;
- gpio_bank_saved[bank].reserved =
- reserved_gpio_map[bank];
-
- gpio = i;
-
- while (mask) {
- if ((mask & 1) && (wakeup_flags_map[gpio] !=
- PM_WAKE_IGNORE)) {
- reserved_gpio_map[gpio_bank(gpio)] |=
- gpio_bit(gpio);
- bfin_gpio_wakeup_type(gpio,
- wakeup_flags_map[gpio]);
- set_gpio_data(gpio, 0); /*Clear*/
- }
- gpio++;
- mask >>= 1;
- }
-
- bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
- gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)];
- }
- }
-
- AWA_DUMMY_READ(maskb_set);
+ set_gpio_maskb(gpio, ctrl);
+ local_irq_restore_hw(flags);
return 0;
}
-void bfin_pm_standby_restore(void)
+int bfin_pm_standby_ctrl(unsigned ctrl)
{
u16 bank, mask, i;
@@ -627,24 +539,10 @@ void bfin_pm_standby_restore(void)
mask = wakeup_map[gpio_bank(i)];
bank = gpio_bank(i);
- if (mask) {
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- *port_fer[bank] = gpio_bank_saved[bank].fer;
-#endif
- gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
- gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
- gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
- gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
- gpio_array[bank]->both = gpio_bank_saved[bank].both;
-
- reserved_gpio_map[bank] =
- gpio_bank_saved[bank].reserved;
- bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
- }
-
- gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb;
+ if (mask)
+ bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl);
}
- AWA_DUMMY_READ(maskb);
+ return 0;
}
void bfin_gpio_pm_hibernate_suspend(void)
@@ -708,16 +606,11 @@ void bfin_gpio_pm_hibernate_restore(void)
#else /* CONFIG_BF54x */
#ifdef CONFIG_PM
-u32 bfin_pm_standby_setup(void)
+int bfin_pm_standby_ctrl(unsigned ctrl)
{
return 0;
}
-void bfin_pm_standby_restore(void)
-{
-
-}
-
void bfin_gpio_pm_hibernate_suspend(void)
{
int i, bank;
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index ed8392c117eaa1d32d0e0623dc12788c4702095b..2c264b51566afa2d7ca45b8ad129fcc8384e89c0 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -32,6 +32,18 @@ EXPORT_SYMBOL(memcmp);
EXPORT_SYMBOL(memmove);
EXPORT_SYMBOL(memchr);
+/*
+ * Because string functions are both inline and exported functions and
+ * folder arch/blackfin/lib is configured as a library path in Makefile,
+ * symbols exported in folder lib is not linked into built-in.o but
+ * inlined only. In order to export string symbols to kernel module
+ * properly, they should be exported here.
+ */
+EXPORT_SYMBOL(strcpy);
+EXPORT_SYMBOL(strncpy);
+EXPORT_SYMBOL(strcmp);
+EXPORT_SYMBOL(strncmp);
+
/*
* libgcc functions - functions that are used internally by the
* compiler... (prototypes are not correct though, but that
diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c
new file mode 100644
index 0000000000000000000000000000000000000000..5cfbaa2982116d3875fbeeeff902cddb7865b491
--- /dev/null
+++ b/arch/blackfin/kernel/dumpstack.c
@@ -0,0 +1,174 @@
+/* Provide basic stack dumping functions
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <linux/kernel.h>
+#include <linux/thread_info.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include <linux/module.h>
+#include <asm/trace.h>
+
+/*
+ * Checks to see if the address pointed to is either a
+ * 16-bit CALL instruction, or a 32-bit CALL instruction
+ */
+static bool is_bfin_call(unsigned short *addr)
+{
+ unsigned int opcode;
+
+ if (!get_instruction(&opcode, addr))
+ return false;
+
+ if ((opcode >= 0x0060 && opcode <= 0x0067) ||
+ (opcode >= 0x0070 && opcode <= 0x0077) ||
+ (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
+ return true;
+
+ return false;
+
+}
+
+void show_stack(struct task_struct *task, unsigned long *stack)
+{
+#ifdef CONFIG_PRINTK
+ unsigned int *addr, *endstack, *fp = 0, *frame;
+ unsigned short *ins_addr;
+ char buf[150];
+ unsigned int i, j, ret_addr, frame_no = 0;
+
+ /*
+ * If we have been passed a specific stack, use that one otherwise
+ * if we have been passed a task structure, use that, otherwise
+ * use the stack of where the variable "stack" exists
+ */
+
+ if (stack == NULL) {
+ if (task) {
+ /* We know this is a kernel stack, so this is the start/end */
+ stack = (unsigned long *)task->thread.ksp;
+ endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
+ } else {
+ /* print out the existing stack info */
+ stack = (unsigned long *)&stack;
+ endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
+ }
+ } else
+ endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
+
+ printk(KERN_NOTICE "Stack info:\n");
+ decode_address(buf, (unsigned int)stack);
+ printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
+
+ if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
+ printk(KERN_NOTICE "Invalid stack pointer\n");
+ return;
+ }
+
+ /* First thing is to look for a frame pointer */
+ for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
+ if (*addr & 0x1)
+ continue;
+ ins_addr = (unsigned short *)*addr;
+ ins_addr--;
+ if (is_bfin_call(ins_addr))
+ fp = addr - 1;
+
+ if (fp) {
+ /* Let's check to see if it is a frame pointer */
+ while (fp >= (addr - 1) && fp < endstack
+ && fp && ((unsigned int) fp & 0x3) == 0)
+ fp = (unsigned int *)*fp;
+ if (fp == 0 || fp == endstack) {
+ fp = addr - 1;
+ break;
+ }
+ fp = 0;
+ }
+ }
+ if (fp) {
+ frame = fp;
+ printk(KERN_NOTICE " FP: (0x%p)\n", fp);
+ } else
+ frame = 0;
+
+ /*
+ * Now that we think we know where things are, we
+ * walk the stack again, this time printing things out
+ * incase there is no frame pointer, we still look for
+ * valid return addresses
+ */
+
+ /* First time print out data, next time, print out symbols */
+ for (j = 0; j <= 1; j++) {
+ if (j)
+ printk(KERN_NOTICE "Return addresses in stack:\n");
+ else
+ printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
+
+ fp = frame;
+ frame_no = 0;
+
+ for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
+ addr < endstack; addr++, i++) {
+
+ ret_addr = 0;
+ if (!j && i % 8 == 0)
+ printk(KERN_NOTICE "%p:", addr);
+
+ /* if it is an odd address, or zero, just skip it */
+ if (*addr & 0x1 || !*addr)
+ goto print;
+
+ ins_addr = (unsigned short *)*addr;
+
+ /* Go back one instruction, and see if it is a CALL */
+ ins_addr--;
+ ret_addr = is_bfin_call(ins_addr);
+ print:
+ if (!j && stack == (unsigned long *)addr)
+ printk("[%08x]", *addr);
+ else if (ret_addr)
+ if (j) {
+ decode_address(buf, (unsigned int)*addr);
+ if (frame == addr) {
+ printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
+ continue;
+ }
+ printk(KERN_NOTICE " address : %s\n", buf);
+ } else
+ printk("<%08x>", *addr);
+ else if (fp == addr) {
+ if (j)
+ frame = addr+1;
+ else
+ printk("(%08x)", *addr);
+
+ fp = (unsigned int *)*addr;
+ frame_no++;
+
+ } else if (!j)
+ printk(" %08x ", *addr);
+ }
+ if (!j)
+ printk("\n");
+ }
+#endif
+}
+EXPORT_SYMBOL(show_stack);
+
+void dump_stack(void)
+{
+ unsigned long stack;
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
+ int tflags;
+#endif
+ trace_buffer_save(tflags);
+ dump_bfin_trace_buffer();
+ show_stack(current, &stack);
+ trace_buffer_restore(tflags);
+}
+EXPORT_SYMBOL(dump_stack);
diff --git a/arch/blackfin/kernel/exception.c b/arch/blackfin/kernel/exception.c
new file mode 100644
index 0000000000000000000000000000000000000000..9208b5fd51864713ad8394a3035e6e2a3c287dcf
--- /dev/null
+++ b/arch/blackfin/kernel/exception.c
@@ -0,0 +1,45 @@
+/* Basic functions for adding/removing custom exception handlers
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <linux/module.h>
+#include <asm/irq_handler.h>
+
+int bfin_request_exception(unsigned int exception, void (*handler)(void))
+{
+ void (*curr_handler)(void);
+
+ if (exception > 0x3F)
+ return -EINVAL;
+
+ curr_handler = ex_table[exception];
+
+ if (curr_handler != ex_replaceable)
+ return -EBUSY;
+
+ ex_table[exception] = handler;
+
+ return 0;
+}
+EXPORT_SYMBOL(bfin_request_exception);
+
+int bfin_free_exception(unsigned int exception, void (*handler)(void))
+{
+ void (*curr_handler)(void);
+
+ if (exception > 0x3F)
+ return -EINVAL;
+
+ curr_handler = ex_table[exception];
+
+ if (curr_handler != handler)
+ return -EBUSY;
+
+ ex_table[exception] = ex_replaceable;
+
+ return 0;
+}
+EXPORT_SYMBOL(bfin_free_exception);
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index 7367aea4ae59ff3cb7af0f9e3b8b18e5f1467aea..08bc44ea688313976e6d54b6cbb679e395271159 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -66,7 +66,7 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
gdb_regs[BFIN_RETN] = regs->retn;
gdb_regs[BFIN_RETE] = regs->rete;
gdb_regs[BFIN_PC] = regs->pc;
- gdb_regs[BFIN_CC] = 0;
+ gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
gdb_regs[BFIN_EXTRA1] = 0;
gdb_regs[BFIN_EXTRA2] = 0;
gdb_regs[BFIN_EXTRA3] = 0;
diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c
new file mode 100644
index 0000000000000000000000000000000000000000..db85bc94334e02c337616dadc4478db559f7bbc4
--- /dev/null
+++ b/arch/blackfin/kernel/pseudodbg.c
@@ -0,0 +1,191 @@
+/* The fake debug assert instructions
+ *
+ * Copyright 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+
+const char * const greg_names[] = {
+ "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
+ "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP",
+ "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3",
+ "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
+ "A0.X", "A0.W", "A1.X", "A1.W", "<res>", "<res>", "ASTAT", "RETS",
+ "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>",
+ "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2",
+ "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT",
+};
+
+static const char *get_allreg_name(int grp, int reg)
+{
+ return greg_names[(grp << 3) | reg];
+}
+
+/*
+ * Unfortunately, the pt_regs structure is not laid out the same way as the
+ * hardware register file, so we need to do some fix ups.
+ *
+ * CYCLES is not stored in the pt_regs structure - so, we just read it from
+ * the hardware.
+ *
+ * Don't support:
+ * - All reserved registers
+ * - All in group 7 are (supervisors only)
+ */
+
+static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
+{
+ long *val = &fp->r0;
+ unsigned long tmp;
+
+ /* Only do Dregs and Pregs for now */
+ if (grp == 5 ||
+ (grp == 4 && (reg == 4 || reg == 5)) ||
+ (grp == 7))
+ return false;
+
+ if (grp == 0 || (grp == 1 && reg < 6))
+ val -= (reg + 8 * grp);
+ else if (grp == 1 && reg == 6)
+ val = &fp->usp;
+ else if (grp == 1 && reg == 7)
+ val = &fp->fp;
+ else if (grp == 2) {
+ val = &fp->i0;
+ val -= reg;
+ } else if (grp == 3 && reg >= 4) {
+ val = &fp->l0;
+ val -= (reg - 4);
+ } else if (grp == 3 && reg < 4) {
+ val = &fp->b0;
+ val -= reg;
+ } else if (grp == 4 && reg < 4) {
+ val = &fp->a0x;
+ val -= reg;
+ } else if (grp == 4 && reg == 6)
+ val = &fp->astat;
+ else if (grp == 4 && reg == 7)
+ val = &fp->rets;
+ else if (grp == 6 && reg < 6) {
+ val = &fp->lc0;
+ val -= reg;
+ } else if (grp == 6 && reg == 6) {
+ __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp));
+ val = &tmp;
+ } else if (grp == 6 && reg == 7) {
+ __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp));
+ val = &tmp;
+ }
+
+ *value = *val;
+ return true;
+
+}
+
+#define PseudoDbg_Assert_opcode 0xf0000000
+#define PseudoDbg_Assert_expected_bits 0
+#define PseudoDbg_Assert_expected_mask 0xffff
+#define PseudoDbg_Assert_regtest_bits 16
+#define PseudoDbg_Assert_regtest_mask 0x7
+#define PseudoDbg_Assert_grp_bits 19
+#define PseudoDbg_Assert_grp_mask 0x7
+#define PseudoDbg_Assert_dbgop_bits 22
+#define PseudoDbg_Assert_dbgop_mask 0x3
+#define PseudoDbg_Assert_dontcare_bits 24
+#define PseudoDbg_Assert_dontcare_mask 0x7
+#define PseudoDbg_Assert_code_bits 27
+#define PseudoDbg_Assert_code_mask 0x1f
+
+/*
+ * DBGA - debug assert
+ */
+bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
+{
+ int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
+ int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
+ int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
+ int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
+ long value;
+
+ if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
+ return false;
+
+ if (!fix_up_reg(fp, &value, grp, regtest))
+ return false;
+
+ if (dbgop == 0 || dbgop == 2) {
+ /* DBGA ( regs_lo , uimm16 ) */
+ /* DBGAL ( regs , uimm16 ) */
+ if (expected != (value & 0xFFFF)) {
+ pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n",
+ get_allreg_name(grp, regtest),
+ expected, (unsigned int)(value & 0xFFFF));
+ return false;
+ }
+
+ } else if (dbgop == 1 || dbgop == 3) {
+ /* DBGA ( regs_hi , uimm16 ) */
+ /* DBGAH ( regs , uimm16 ) */
+ if (expected != ((value >> 16) & 0xFFFF)) {
+ pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n",
+ get_allreg_name(grp, regtest),
+ expected, (unsigned int)((value >> 16) & 0xFFFF));
+ return false;
+ }
+ }
+
+ fp->pc += 4;
+ return true;
+}
+
+#define PseudoDbg_opcode 0xf8000000
+#define PseudoDbg_reg_bits 0
+#define PseudoDbg_reg_mask 0x7
+#define PseudoDbg_grp_bits 3
+#define PseudoDbg_grp_mask 0x7
+#define PseudoDbg_fn_bits 6
+#define PseudoDbg_fn_mask 0x3
+#define PseudoDbg_code_bits 8
+#define PseudoDbg_code_mask 0xff
+
+/*
+ * DBG - debug (dump a register value out)
+ */
+bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
+{
+ int grp, fn, reg;
+ long value, value1;
+
+ if ((opcode & 0xFF000000) != PseudoDbg_opcode)
+ return false;
+
+ opcode >>= 16;
+ grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
+ fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
+ reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
+
+ if (fn == 3 && (reg == 0 || reg == 1)) {
+ if (!fix_up_reg(fp, &value, 4, 2 * reg))
+ return false;
+ if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1))
+ return false;
+
+ pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1);
+ fp->pc += 2;
+ return true;
+
+ } else if (fn == 0) {
+ if (!fix_up_reg(fp, &value, grp, reg))
+ return false;
+
+ pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value);
+ fp->pc += 2;
+ return true;
+ }
+
+ return false;
+}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 8e2efceb364b8752b48ae63c97451ee0ee58a629..d37a397f43f5eacab8517c6c83fd2cf50e1905da 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@@ -925,7 +925,7 @@ void __init setup_arch(char **cmdline_p)
else if (_bfin_swrst & RESET_SOFTWARE)
printk(KERN_NOTICE "Reset caused by Software reset\n");
- printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n");
+ printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
if (bfin_compiled_revid() == 0xffff)
printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
else if (bfin_compiled_revid() == -1)
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index 2e7f8e10bf87109083f43f73411327ae5223f724..bdc1e2f0da32383420a46ef6c1e3fe93a805c0ea 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -47,3 +47,26 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr,
}
EXPORT_SYMBOL(get_fb_unmapped_area);
#endif
+
+/* Needed for legacy userspace atomic emulation */
+static DEFINE_SPINLOCK(bfin_spinlock_lock);
+
+#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
+__attribute__((l1_text))
+#endif
+asmlinkage int sys_bfin_spinlock(int *p)
+{
+ int ret, tmp = 0;
+
+ spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
+ ret = get_user(tmp, p);
+ if (likely(ret == 0)) {
+ if (unlikely(tmp))
+ ret = 1;
+ else
+ put_user(1, p);
+ }
+ spin_unlock(&bfin_spinlock_lock);
+
+ return ret;
+}
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
new file mode 100644
index 0000000000000000000000000000000000000000..59fcdf6b0138532604be9d8de4d1c93260029349
--- /dev/null
+++ b/arch/blackfin/kernel/trace.c
@@ -0,0 +1,981 @@
+/* provide some functions which dump the trace buffer, in a nice way for people
+ * to read it, and understand what is going on
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <linux/kernel.h>
+#include <linux/hardirq.h>
+#include <linux/thread_info.h>
+#include <linux/mm.h>
+#include <linux/uaccess.h>
+#include <linux/module.h>
+#include <linux/kallsyms.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <asm/dma.h>
+#include <asm/trace.h>
+#include <asm/fixed_code.h>
+#include <asm/traps.h>
+#include <asm/irq_handler.h>
+
+void decode_address(char *buf, unsigned long address)
+{
+ struct task_struct *p;
+ struct mm_struct *mm;
+ unsigned long flags, offset;
+ unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
+ struct rb_node *n;
+
+#ifdef CONFIG_KALLSYMS
+ unsigned long symsize;
+ const char *symname;
+ char *modname;
+ char *delim = ":";
+ char namebuf[128];
+#endif
+
+ buf += sprintf(buf, "<0x%08lx> ", address);
+
+#ifdef CONFIG_KALLSYMS
+ /* look up the address and see if we are in kernel space */
+ symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
+
+ if (symname) {
+ /* yeah! kernel space! */
+ if (!modname)
+ modname = delim = "";
+ sprintf(buf, "{ %s%s%s%s + 0x%lx }",
+ delim, modname, delim, symname,
+ (unsigned long)offset);
+ return;
+ }
+#endif
+
+ if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
+ /* Problem in fixed code section? */
+ strcat(buf, "/* Maybe fixed code section */");
+ return;
+
+ } else if (address < CONFIG_BOOT_LOAD) {
+ /* Problem somewhere before the kernel start address */
+ strcat(buf, "/* Maybe null pointer? */");
+ return;
+
+ } else if (address >= COREMMR_BASE) {
+ strcat(buf, "/* core mmrs */");
+ return;
+
+ } else if (address >= SYSMMR_BASE) {
+ strcat(buf, "/* system mmrs */");
+ return;
+
+ } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
+ strcat(buf, "/* on-chip L1 ROM */");
+ return;
+
+ } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
+ strcat(buf, "/* on-chip scratchpad */");
+ return;
+
+ } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
+ strcat(buf, "/* unconnected memory */");
+ return;
+
+ } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
+ strcat(buf, "/* reserved memory */");
+ return;
+
+ } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
+ strcat(buf, "/* on-chip Data Bank A */");
+ return;
+
+ } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
+ strcat(buf, "/* on-chip Data Bank B */");
+ return;
+ }
+
+ /*
+ * Don't walk any of the vmas if we are oopsing, it has been known
+ * to cause problems - corrupt vmas (kernel crashes) cause double faults
+ */
+ if (oops_in_progress) {
+ strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
+ return;
+ }
+
+ /* looks like we're off in user-land, so let's walk all the
+ * mappings of all our processes and see if we can't be a whee
+ * bit more specific
+ */
+ write_lock_irqsave(&tasklist_lock, flags);
+ for_each_process(p) {
+ mm = (in_atomic ? p->mm : get_task_mm(p));
+ if (!mm)
+ continue;
+
+ if (!down_read_trylock(&mm->mmap_sem)) {
+ if (!in_atomic)
+ mmput(mm);
+ continue;
+ }
+
+ for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
+ struct vm_area_struct *vma;
+
+ vma = rb_entry(n, struct vm_area_struct, vm_rb);
+
+ if (address >= vma->vm_start && address < vma->vm_end) {
+ char _tmpbuf[256];
+ char *name = p->comm;
+ struct file *file = vma->vm_file;
+
+ if (file) {
+ char *d_name = d_path(&file->f_path, _tmpbuf,
+ sizeof(_tmpbuf));
+ if (!IS_ERR(d_name))
+ name = d_name;
+ }
+
+ /* FLAT does not have its text aligned to the start of
+ * the map while FDPIC ELF does ...
+ */
+
+ /* before we can check flat/fdpic, we need to
+ * make sure current is valid
+ */
+ if ((unsigned long)current >= FIXED_CODE_START &&
+ !((unsigned long)current & 0x3)) {
+ if (current->mm &&
+ (address > current->mm->start_code) &&
+ (address < current->mm->end_code))
+ offset = address - current->mm->start_code;
+ else
+ offset = (address - vma->vm_start) +
+ (vma->vm_pgoff << PAGE_SHIFT);
+
+ sprintf(buf, "[ %s + 0x%lx ]", name, offset);
+ } else
+ sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
+ name, vma->vm_start, vma->vm_end);
+
+ up_read(&mm->mmap_sem);
+ if (!in_atomic)
+ mmput(mm);
+
+ if (buf[0] == '\0')
+ sprintf(buf, "[ %s ] dynamic memory", name);
+
+ goto done;
+ }
+ }
+
+ up_read(&mm->mmap_sem);
+ if (!in_atomic)
+ mmput(mm);
+ }
+
+ /*
+ * we were unable to find this address anywhere,
+ * or some MMs were skipped because they were in use.
+ */
+ sprintf(buf, "/* kernel dynamic memory */");
+
+done:
+ write_unlock_irqrestore(&tasklist_lock, flags);
+}
+
+#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
+
+/*
+ * Similar to get_user, do some address checking, then dereference
+ * Return true on success, false on bad address
+ */
+bool get_mem16(unsigned short *val, unsigned short *address)
+{
+ unsigned long addr = (unsigned long)address;
+
+ /* Check for odd addresses */
+ if (addr & 0x1)
+ return false;
+
+ switch (bfin_mem_access_type(addr, 2)) {
+ case BFIN_MEM_ACCESS_CORE:
+ case BFIN_MEM_ACCESS_CORE_ONLY:
+ *val = *address;
+ return true;
+ case BFIN_MEM_ACCESS_DMA:
+ dma_memcpy(val, address, 2);
+ return true;
+ case BFIN_MEM_ACCESS_ITEST:
+ isram_memcpy(val, address, 2);
+ return true;
+ default: /* invalid access */
+ return false;
+ }
+}
+
+bool get_instruction(unsigned int *val, unsigned short *address)
+{
+ unsigned long addr = (unsigned long)address;
+ unsigned short opcode0, opcode1;
+
+ /* Check for odd addresses */
+ if (addr & 0x1)
+ return false;
+
+ /* MMR region will never have instructions */
+ if (addr >= SYSMMR_BASE)
+ return false;
+
+ /* Scratchpad will never have instructions */
+ if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
+ return false;
+
+ /* Data banks will never have instructions */
+ if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
+ return false;
+
+ if (!get_mem16(&opcode0, address))
+ return false;
+
+ /* was this a 32-bit instruction? If so, get the next 16 bits */
+ if ((opcode0 & 0xc000) == 0xc000) {
+ if (!get_mem16(&opcode1, address + 1))
+ return false;
+ *val = (opcode0 << 16) + opcode1;
+ } else
+ *val = opcode0;
+
+ return true;
+}
+
+#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
+/*
+ * decode the instruction if we are printing out the trace, as it
+ * makes things easier to follow, without running it through objdump
+ * Decode the change of flow, and the common load/store instructions
+ * which are the main cause for faults, and discontinuities in the trace
+ * buffer.
+ */
+
+#define ProgCtrl_opcode 0x0000
+#define ProgCtrl_poprnd_bits 0
+#define ProgCtrl_poprnd_mask 0xf
+#define ProgCtrl_prgfunc_bits 4
+#define ProgCtrl_prgfunc_mask 0xf
+#define ProgCtrl_code_bits 8
+#define ProgCtrl_code_mask 0xff
+
+static void decode_ProgCtrl_0(unsigned int opcode)
+{
+ int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
+ int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
+
+ if (prgfunc == 0 && poprnd == 0)
+ pr_cont("NOP");
+ else if (prgfunc == 1 && poprnd == 0)
+ pr_cont("RTS");
+ else if (prgfunc == 1 && poprnd == 1)
+ pr_cont("RTI");
+ else if (prgfunc == 1 && poprnd == 2)
+ pr_cont("RTX");
+ else if (prgfunc == 1 && poprnd == 3)
+ pr_cont("RTN");
+ else if (prgfunc == 1 && poprnd == 4)
+ pr_cont("RTE");
+ else if (prgfunc == 2 && poprnd == 0)
+ pr_cont("IDLE");
+ else if (prgfunc == 2 && poprnd == 3)
+ pr_cont("CSYNC");
+ else if (prgfunc == 2 && poprnd == 4)
+ pr_cont("SSYNC");
+ else if (prgfunc == 2 && poprnd == 5)
+ pr_cont("EMUEXCPT");
+ else if (prgfunc == 3)
+ pr_cont("CLI R%i", poprnd);
+ else if (prgfunc == 4)
+ pr_cont("STI R%i", poprnd);
+ else if (prgfunc == 5)
+ pr_cont("JUMP (P%i)", poprnd);
+ else if (prgfunc == 6)
+ pr_cont("CALL (P%i)", poprnd);
+ else if (prgfunc == 7)
+ pr_cont("CALL (PC + P%i)", poprnd);
+ else if (prgfunc == 8)
+ pr_cont("JUMP (PC + P%i", poprnd);
+ else if (prgfunc == 9)
+ pr_cont("RAISE %i", poprnd);
+ else if (prgfunc == 10)
+ pr_cont("EXCPT %i", poprnd);
+ else
+ pr_cont("0x%04x", opcode);
+
+}
+
+#define BRCC_opcode 0x1000
+#define BRCC_offset_bits 0
+#define BRCC_offset_mask 0x3ff
+#define BRCC_B_bits 10
+#define BRCC_B_mask 0x1
+#define BRCC_T_bits 11
+#define BRCC_T_mask 0x1
+#define BRCC_code_bits 12
+#define BRCC_code_mask 0xf
+
+static void decode_BRCC_0(unsigned int opcode)
+{
+ int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
+ int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
+
+ pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
+}
+
+#define CALLa_opcode 0xe2000000
+#define CALLa_addr_bits 0
+#define CALLa_addr_mask 0xffffff
+#define CALLa_S_bits 24
+#define CALLa_S_mask 0x1
+#define CALLa_code_bits 25
+#define CALLa_code_mask 0x7f
+
+static void decode_CALLa_0(unsigned int opcode)
+{
+ int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
+
+ if (S)
+ pr_cont("CALL pcrel");
+ else
+ pr_cont("JUMP.L");
+}
+
+#define LoopSetup_opcode 0xe0800000
+#define LoopSetup_eoffset_bits 0
+#define LoopSetup_eoffset_mask 0x3ff
+#define LoopSetup_dontcare_bits 10
+#define LoopSetup_dontcare_mask 0x3
+#define LoopSetup_reg_bits 12
+#define LoopSetup_reg_mask 0xf
+#define LoopSetup_soffset_bits 16
+#define LoopSetup_soffset_mask 0xf
+#define LoopSetup_c_bits 20
+#define LoopSetup_c_mask 0x1
+#define LoopSetup_rop_bits 21
+#define LoopSetup_rop_mask 0x3
+#define LoopSetup_code_bits 23
+#define LoopSetup_code_mask 0x1ff
+
+static void decode_LoopSetup_0(unsigned int opcode)
+{
+ int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
+ int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
+ int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
+
+ pr_cont("LSETUP <> LC%i", c);
+ if ((rop & 1) == 1)
+ pr_cont("= P%i", reg);
+ if ((rop & 2) == 2)
+ pr_cont(" >> 0x1");
+}
+
+#define DspLDST_opcode 0x9c00
+#define DspLDST_reg_bits 0
+#define DspLDST_reg_mask 0x7
+#define DspLDST_i_bits 3
+#define DspLDST_i_mask 0x3
+#define DspLDST_m_bits 5
+#define DspLDST_m_mask 0x3
+#define DspLDST_aop_bits 7
+#define DspLDST_aop_mask 0x3
+#define DspLDST_W_bits 9
+#define DspLDST_W_mask 0x1
+#define DspLDST_code_bits 10
+#define DspLDST_code_mask 0x3f
+
+static void decode_dspLDST_0(unsigned int opcode)
+{
+ int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
+ int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
+ int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
+ int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
+ int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
+
+ if (W == 0) {
+ pr_cont("R%i", reg);
+ switch (m) {
+ case 0:
+ pr_cont(" = ");
+ break;
+ case 1:
+ pr_cont(".L = ");
+ break;
+ case 2:
+ pr_cont(".W = ");
+ break;
+ }
+ }
+
+ pr_cont("[ I%i", i);
+
+ switch (aop) {
+ case 0:
+ pr_cont("++ ]");
+ break;
+ case 1:
+ pr_cont("-- ]");
+ break;
+ }
+
+ if (W == 1) {
+ pr_cont(" = R%i", reg);
+ switch (m) {
+ case 1:
+ pr_cont(".L = ");
+ break;
+ case 2:
+ pr_cont(".W = ");
+ break;
+ }
+ }
+}
+
+#define LDST_opcode 0x9000
+#define LDST_reg_bits 0
+#define LDST_reg_mask 0x7
+#define LDST_ptr_bits 3
+#define LDST_ptr_mask 0x7
+#define LDST_Z_bits 6
+#define LDST_Z_mask 0x1
+#define LDST_aop_bits 7
+#define LDST_aop_mask 0x3
+#define LDST_W_bits 9
+#define LDST_W_mask 0x1
+#define LDST_sz_bits 10
+#define LDST_sz_mask 0x3
+#define LDST_code_bits 12
+#define LDST_code_mask 0xf
+
+static void decode_LDST_0(unsigned int opcode)
+{
+ int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
+ int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
+ int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
+ int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
+ int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
+ int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
+
+ if (W == 0)
+ pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
+
+ switch (sz) {
+ case 1:
+ pr_cont("W");
+ break;
+ case 2:
+ pr_cont("B");
+ break;
+ }
+
+ pr_cont("[P%i", ptr);
+
+ switch (aop) {
+ case 0:
+ pr_cont("++");
+ break;
+ case 1:
+ pr_cont("--");
+ break;
+ }
+ pr_cont("]");
+
+ if (W == 1)
+ pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
+
+ if (sz) {
+ if (Z)
+ pr_cont(" (X)");
+ else
+ pr_cont(" (Z)");
+ }
+}
+
+#define LDSTii_opcode 0xa000
+#define LDSTii_reg_bit 0
+#define LDSTii_reg_mask 0x7
+#define LDSTii_ptr_bit 3
+#define LDSTii_ptr_mask 0x7
+#define LDSTii_offset_bit 6
+#define LDSTii_offset_mask 0xf
+#define LDSTii_op_bit 10
+#define LDSTii_op_mask 0x3
+#define LDSTii_W_bit 12
+#define LDSTii_W_mask 0x1
+#define LDSTii_code_bit 13
+#define LDSTii_code_mask 0x7
+
+static void decode_LDSTii_0(unsigned int opcode)
+{
+ int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
+ int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
+ int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
+ int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
+ int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
+
+ if (W == 0) {
+ pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
+ op == 1 || op == 2 ? "" : "W", ptr, offset);
+ if (op == 2)
+ pr_cont("(Z)");
+ if (op == 3)
+ pr_cont("(X)");
+ } else {
+ pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
+ offset, op == 3 ? "P" : "R", reg);
+ }
+}
+
+#define LDSTidxI_opcode 0xe4000000
+#define LDSTidxI_offset_bits 0
+#define LDSTidxI_offset_mask 0xffff
+#define LDSTidxI_reg_bits 16
+#define LDSTidxI_reg_mask 0x7
+#define LDSTidxI_ptr_bits 19
+#define LDSTidxI_ptr_mask 0x7
+#define LDSTidxI_sz_bits 22
+#define LDSTidxI_sz_mask 0x3
+#define LDSTidxI_Z_bits 24
+#define LDSTidxI_Z_mask 0x1
+#define LDSTidxI_W_bits 25
+#define LDSTidxI_W_mask 0x1
+#define LDSTidxI_code_bits 26
+#define LDSTidxI_code_mask 0x3f
+
+static void decode_LDSTidxI_0(unsigned int opcode)
+{
+ int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
+ int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
+ int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
+ int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
+ int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
+ int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
+
+ if (W == 0)
+ pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
+
+ if (sz == 1)
+ pr_cont("W");
+ if (sz == 2)
+ pr_cont("B");
+
+ pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
+ (offset & 0x1f) << 2);
+
+ if (W == 0 && sz != 0) {
+ if (Z)
+ pr_cont("(X)");
+ else
+ pr_cont("(Z)");
+ }
+
+ if (W == 1)
+ pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
+
+}
+
+static void decode_opcode(unsigned int opcode)
+{
+#ifdef CONFIG_BUG
+ if (opcode == BFIN_BUG_OPCODE)
+ pr_cont("BUG");
+ else
+#endif
+ if ((opcode & 0xffffff00) == ProgCtrl_opcode)
+ decode_ProgCtrl_0(opcode);
+ else if ((opcode & 0xfffff000) == BRCC_opcode)
+ decode_BRCC_0(opcode);
+ else if ((opcode & 0xfffff000) == 0x2000)
+ pr_cont("JUMP.S");
+ else if ((opcode & 0xfe000000) == CALLa_opcode)
+ decode_CALLa_0(opcode);
+ else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
+ decode_LoopSetup_0(opcode);
+ else if ((opcode & 0xfffffc00) == DspLDST_opcode)
+ decode_dspLDST_0(opcode);
+ else if ((opcode & 0xfffff000) == LDST_opcode)
+ decode_LDST_0(opcode);
+ else if ((opcode & 0xffffe000) == LDSTii_opcode)
+ decode_LDSTii_0(opcode);
+ else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
+ decode_LDSTidxI_0(opcode);
+ else if (opcode & 0xffff0000)
+ pr_cont("0x%08x", opcode);
+ else
+ pr_cont("0x%04x", opcode);
+}
+
+#define BIT_MULTI_INS 0x08000000
+static void decode_instruction(unsigned short *address)
+{
+ unsigned int opcode;
+
+ if (!get_instruction(&opcode, address))
+ return;
+
+ decode_opcode(opcode);
+
+ /* If things are a 32-bit instruction, it has the possibility of being
+ * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
+ * This test collidates with the unlink instruction, so disallow that
+ */
+ if ((opcode & 0xc0000000) == 0xc0000000 &&
+ (opcode & BIT_MULTI_INS) &&
+ (opcode & 0xe8000000) != 0xe8000000) {
+ pr_cont(" || ");
+ if (!get_instruction(&opcode, address + 2))
+ return;
+ decode_opcode(opcode);
+ pr_cont(" || ");
+ if (!get_instruction(&opcode, address + 3))
+ return;
+ decode_opcode(opcode);
+ }
+}
+#endif
+
+void dump_bfin_trace_buffer(void)
+{
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
+ int tflags, i = 0, fault = 0;
+ char buf[150];
+ unsigned short *addr;
+ unsigned int cpu = raw_smp_processor_id();
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+ int j, index;
+#endif
+
+ trace_buffer_save(tflags);
+
+ pr_notice("Hardware Trace:\n");
+
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+ pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
+#endif
+
+ if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
+ for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
+ addr = (unsigned short *)bfin_read_TBUF();
+ decode_address(buf, (unsigned long)addr);
+ pr_notice("%4i Target : %s\n", i, buf);
+ /* Normally, the faulting instruction doesn't go into
+ * the trace buffer, (since it doesn't commit), so
+ * we print out the fault address here
+ */
+ if (!fault && addr == ((unsigned short *)evt_ivhw)) {
+ addr = (unsigned short *)bfin_read_TBUF();
+ decode_address(buf, (unsigned long)addr);
+ pr_notice(" FAULT : %s ", buf);
+ decode_instruction(addr);
+ pr_cont("\n");
+ fault = 1;
+ continue;
+ }
+ if (!fault && addr == (unsigned short *)trap &&
+ (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
+ decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
+ pr_notice(" FAULT : %s ", buf);
+ decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
+ pr_cont("\n");
+ fault = 1;
+ }
+ addr = (unsigned short *)bfin_read_TBUF();
+ decode_address(buf, (unsigned long)addr);
+ pr_notice(" Source : %s ", buf);
+ decode_instruction(addr);
+ pr_cont("\n");
+ }
+ }
+
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+ if (trace_buff_offset)
+ index = trace_buff_offset / 4;
+ else
+ index = EXPAND_LEN;
+
+ j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
+ while (j) {
+ decode_address(buf, software_trace_buff[index]);
+ pr_notice("%4i Target : %s\n", i, buf);
+ index -= 1;
+ if (index < 0)
+ index = EXPAND_LEN;
+ decode_address(buf, software_trace_buff[index]);
+ pr_notice(" Source : %s ", buf);
+ decode_instruction((unsigned short *)software_trace_buff[index]);
+ pr_cont("\n");
+ index -= 1;
+ if (index < 0)
+ index = EXPAND_LEN;
+ j--;
+ i++;
+ }
+#endif
+
+ trace_buffer_restore(tflags);
+#endif
+}
+EXPORT_SYMBOL(dump_bfin_trace_buffer);
+
+void dump_bfin_process(struct pt_regs *fp)
+{
+ /* We should be able to look at fp->ipend, but we don't push it on the
+ * stack all the time, so do this until we fix that */
+ unsigned int context = bfin_read_IPEND();
+
+ if (oops_in_progress)
+ pr_emerg("Kernel OOPS in progress\n");
+
+ if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
+ pr_notice("HW Error context\n");
+ else if (context & 0x0020)
+ pr_notice("Deferred Exception context\n");
+ else if (context & 0x3FC0)
+ pr_notice("Interrupt context\n");
+ else if (context & 0x4000)
+ pr_notice("Deferred Interrupt context\n");
+ else if (context & 0x8000)
+ pr_notice("Kernel process context\n");
+
+ /* Because we are crashing, and pointers could be bad, we check things
+ * pretty closely before we use them
+ */
+ if ((unsigned long)current >= FIXED_CODE_START &&
+ !((unsigned long)current & 0x3) && current->pid) {
+ pr_notice("CURRENT PROCESS:\n");
+ if (current->comm >= (char *)FIXED_CODE_START)
+ pr_notice("COMM=%s PID=%d",
+ current->comm, current->pid);
+ else
+ pr_notice("COMM= invalid");
+
+ pr_cont(" CPU=%d\n", current_thread_info()->cpu);
+ if (!((unsigned long)current->mm & 0x3) &&
+ (unsigned long)current->mm >= FIXED_CODE_START) {
+ pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
+ (void *)current->mm->start_code,
+ (void *)current->mm->end_code,
+ (void *)current->mm->start_data,
+ (void *)current->mm->end_data);
+ pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
+ (void *)current->mm->end_data,
+ (void *)current->mm->brk,
+ (void *)current->mm->start_stack);
+ } else
+ pr_notice("invalid mm\n");
+ } else
+ pr_notice("No Valid process in current context\n");
+}
+
+void dump_bfin_mem(struct pt_regs *fp)
+{
+ unsigned short *addr, *erraddr, val = 0, err = 0;
+ char sti = 0, buf[6];
+
+ erraddr = (void *)fp->pc;
+
+ pr_notice("return address: [0x%p]; contents of:", erraddr);
+
+ for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
+ addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
+ addr++) {
+ if (!((unsigned long)addr & 0xF))
+ pr_notice("0x%p: ", addr);
+
+ if (!get_mem16(&val, addr)) {
+ val = 0;
+ sprintf(buf, "????");
+ } else
+ sprintf(buf, "%04x", val);
+
+ if (addr == erraddr) {
+ pr_cont("[%s]", buf);
+ err = val;
+ } else
+ pr_cont(" %s ", buf);
+
+ /* Do any previous instructions turn on interrupts? */
+ if (addr <= erraddr && /* in the past */
+ ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
+ val == 0x017b)) /* [SP++] = RETI */
+ sti = 1;
+ }
+
+ pr_cont("\n");
+
+ /* Hardware error interrupts can be deferred */
+ if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
+ oops_in_progress)){
+ pr_notice("Looks like this was a deferred error - sorry\n");
+#ifndef CONFIG_DEBUG_HWERR
+ pr_notice("The remaining message may be meaningless\n");
+ pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
+#else
+ /* If we are handling only one peripheral interrupt
+ * and current mm and pid are valid, and the last error
+ * was in that user space process's text area
+ * print it out - because that is where the problem exists
+ */
+ if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
+ (current->pid && current->mm)) {
+ /* And the last RETI points to the current userspace context */
+ if ((fp + 1)->pc >= current->mm->start_code &&
+ (fp + 1)->pc <= current->mm->end_code) {
+ pr_notice("It might be better to look around here :\n");
+ pr_notice("-------------------------------------------\n");
+ show_regs(fp + 1);
+ pr_notice("-------------------------------------------\n");
+ }
+ }
+#endif
+ }
+}
+
+void show_regs(struct pt_regs *fp)
+{
+ char buf[150];
+ struct irqaction *action;
+ unsigned int i;
+ unsigned long flags = 0;
+ unsigned int cpu = raw_smp_processor_id();
+ unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
+
+ pr_notice("\n");
+ if (CPUID != bfin_cpuid())
+ pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
+ "but running on:0x%04x (Rev %d)\n",
+ CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
+
+ pr_notice("ADSP-%s-0.%d",
+ CPU, bfin_compiled_revid());
+
+ if (bfin_compiled_revid() != bfin_revid())
+ pr_cont("(Detected 0.%d)", bfin_revid());
+
+ pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
+ get_cclk()/1000000, get_sclk()/1000000,
+#ifdef CONFIG_MPU
+ "mpu on"
+#else
+ "mpu off"
+#endif
+ );
+
+ pr_notice("%s", linux_banner);
+
+ pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
+ pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
+ (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
+ if (fp->ipend & EVT_IRPTEN)
+ pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
+ if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
+ EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
+ pr_notice(" Peripheral interrupts masked off\n");
+ if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
+ pr_notice(" Kernel interrupts masked off\n");
+ if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
+ pr_notice(" HWERRCAUSE: 0x%lx\n",
+ (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
+#ifdef EBIU_ERRMST
+ /* If the error was from the EBIU, print it out */
+ if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
+ pr_notice(" EBIU Error Reason : 0x%04x\n",
+ bfin_read_EBIU_ERRMST());
+ pr_notice(" EBIU Error Address : 0x%08x\n",
+ bfin_read_EBIU_ERRADD());
+ }
+#endif
+ }
+ pr_notice(" EXCAUSE : 0x%lx\n",
+ fp->seqstat & SEQSTAT_EXCAUSE);
+ for (i = 2; i <= 15 ; i++) {
+ if (fp->ipend & (1 << i)) {
+ if (i != 4) {
+ decode_address(buf, bfin_read32(EVT0 + 4*i));
+ pr_notice(" physical IVG%i asserted : %s\n", i, buf);
+ } else
+ pr_notice(" interrupts disabled\n");
+ }
+ }
+
+ /* if no interrupts are going off, don't print this out */
+ if (fp->ipend & ~0x3F) {
+ for (i = 0; i < (NR_IRQS - 1); i++) {
+ if (!in_atomic)
+ raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
+
+ action = irq_desc[i].action;
+ if (!action)
+ goto unlock;
+
+ decode_address(buf, (unsigned int)action->handler);
+ pr_notice(" logical irq %3d mapped : %s", i, buf);
+ for (action = action->next; action; action = action->next) {
+ decode_address(buf, (unsigned int)action->handler);
+ pr_cont(", %s", buf);
+ }
+ pr_cont("\n");
+unlock:
+ if (!in_atomic)
+ raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+ }
+ }
+
+ decode_address(buf, fp->rete);
+ pr_notice(" RETE: %s\n", buf);
+ decode_address(buf, fp->retn);
+ pr_notice(" RETN: %s\n", buf);
+ decode_address(buf, fp->retx);
+ pr_notice(" RETX: %s\n", buf);
+ decode_address(buf, fp->rets);
+ pr_notice(" RETS: %s\n", buf);
+ decode_address(buf, fp->pc);
+ pr_notice(" PC : %s\n", buf);
+
+ if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
+ (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
+ decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
+ pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
+ decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
+ pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
+ }
+
+ pr_notice("PROCESSOR STATE:\n");
+ pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
+ fp->r0, fp->r1, fp->r2, fp->r3);
+ pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
+ fp->r4, fp->r5, fp->r6, fp->r7);
+ pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
+ fp->p0, fp->p1, fp->p2, fp->p3);
+ pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
+ fp->p4, fp->p5, fp->fp, (long)fp);
+ pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
+ fp->lb0, fp->lt0, fp->lc0);
+ pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
+ fp->lb1, fp->lt1, fp->lc1);
+ pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
+ fp->b0, fp->l0, fp->m0, fp->i0);
+ pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
+ fp->b1, fp->l1, fp->m1, fp->i1);
+ pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
+ fp->b2, fp->l2, fp->m2, fp->i2);
+ pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
+ fp->b3, fp->l3, fp->m3, fp->i3);
+ pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
+ fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+ pr_notice("USP : %08lx ASTAT: %08lx\n",
+ rdusp(), fp->astat);
+
+ pr_notice("\n");
+}
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index ba70c4bc2699e7a288b36a591930106b23d84d32..59c1df75e4de9519d61070142b62f3b1eb90ef5a 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -1,25 +1,22 @@
/*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Main exception handling logic.
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#include <linux/bug.h>
#include <linux/uaccess.h>
-#include <linux/interrupt.h>
#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/fs.h>
-#include <linux/rbtree.h>
#include <asm/traps.h>
-#include <asm/cacheflush.h>
#include <asm/cplb.h>
-#include <asm/dma.h>
#include <asm/blackfin.h>
#include <asm/irq_handler.h>
#include <linux/irq.h>
#include <asm/trace.h>
#include <asm/fixed_code.h>
+#include <asm/pseudo_instructions.h>
#ifdef CONFIG_KGDB
# include <linux/kgdb.h>
@@ -62,194 +59,6 @@ void __init trap_init(void)
CSYNC();
}
-static void decode_address(char *buf, unsigned long address)
-{
-#ifdef CONFIG_DEBUG_VERBOSE
- struct task_struct *p;
- struct mm_struct *mm;
- unsigned long flags, offset;
- unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
- struct rb_node *n;
-
-#ifdef CONFIG_KALLSYMS
- unsigned long symsize;
- const char *symname;
- char *modname;
- char *delim = ":";
- char namebuf[128];
-#endif
-
- buf += sprintf(buf, "<0x%08lx> ", address);
-
-#ifdef CONFIG_KALLSYMS
- /* look up the address and see if we are in kernel space */
- symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
-
- if (symname) {
- /* yeah! kernel space! */
- if (!modname)
- modname = delim = "";
- sprintf(buf, "{ %s%s%s%s + 0x%lx }",
- delim, modname, delim, symname,
- (unsigned long)offset);
- return;
- }
-#endif
-
- if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
- /* Problem in fixed code section? */
- strcat(buf, "/* Maybe fixed code section */");
- return;
-
- } else if (address < CONFIG_BOOT_LOAD) {
- /* Problem somewhere before the kernel start address */
- strcat(buf, "/* Maybe null pointer? */");
- return;
-
- } else if (address >= COREMMR_BASE) {
- strcat(buf, "/* core mmrs */");
- return;
-
- } else if (address >= SYSMMR_BASE) {
- strcat(buf, "/* system mmrs */");
- return;
-
- } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
- strcat(buf, "/* on-chip L1 ROM */");
- return;
- }
-
- /*
- * Don't walk any of the vmas if we are oopsing, it has been known
- * to cause problems - corrupt vmas (kernel crashes) cause double faults
- */
- if (oops_in_progress) {
- strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
- return;
- }
-
- /* looks like we're off in user-land, so let's walk all the
- * mappings of all our processes and see if we can't be a whee
- * bit more specific
- */
- write_lock_irqsave(&tasklist_lock, flags);
- for_each_process(p) {
- mm = (in_atomic ? p->mm : get_task_mm(p));
- if (!mm)
- continue;
-
- if (!down_read_trylock(&mm->mmap_sem)) {
- if (!in_atomic)
- mmput(mm);
- continue;
- }
-
- for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
- struct vm_area_struct *vma;
-
- vma = rb_entry(n, struct vm_area_struct, vm_rb);
-
- if (address >= vma->vm_start && address < vma->vm_end) {
- char _tmpbuf[256];
- char *name = p->comm;
- struct file *file = vma->vm_file;
-
- if (file) {
- char *d_name = d_path(&file->f_path, _tmpbuf,
- sizeof(_tmpbuf));
- if (!IS_ERR(d_name))
- name = d_name;
- }
-
- /* FLAT does not have its text aligned to the start of
- * the map while FDPIC ELF does ...
- */
-
- /* before we can check flat/fdpic, we need to
- * make sure current is valid
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3)) {
- if (current->mm &&
- (address > current->mm->start_code) &&
- (address < current->mm->end_code))
- offset = address - current->mm->start_code;
- else
- offset = (address - vma->vm_start) +
- (vma->vm_pgoff << PAGE_SHIFT);
-
- sprintf(buf, "[ %s + 0x%lx ]", name, offset);
- } else
- sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
- name, vma->vm_start, vma->vm_end);
-
- up_read(&mm->mmap_sem);
- if (!in_atomic)
- mmput(mm);
-
- if (buf[0] == '\0')
- sprintf(buf, "[ %s ] dynamic memory", name);
-
- goto done;
- }
- }
-
- up_read(&mm->mmap_sem);
- if (!in_atomic)
- mmput(mm);
- }
-
- /*
- * we were unable to find this address anywhere,
- * or some MMs were skipped because they were in use.
- */
- sprintf(buf, "/* kernel dynamic memory */");
-
-done:
- write_unlock_irqrestore(&tasklist_lock, flags);
-#else
- sprintf(buf, " ");
-#endif
-}
-
-asmlinkage void double_fault_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
- trace_buffer_save(j);
-#endif
-
- console_verbose();
- oops_in_progress = 1;
-#ifdef CONFIG_DEBUG_VERBOSE
- printk(KERN_EMERG "Double Fault\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
- unsigned int cpu = raw_smp_processor_id();
- char buf[150];
- decode_address(buf, cpu_pda[cpu].retx_doublefault);
- printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
- (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
- decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
-
- decode_address(buf, fp->retx);
- printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
- } else
-#endif
- {
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-#endif
- panic("Double Fault - unrecoverable event");
-
-}
-
static int kernel_mode_regs(struct pt_regs *regs)
{
return regs->ipend & 0xffc0;
@@ -259,6 +68,9 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
{
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
int j;
+#endif
+#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
+ int opcode;
#endif
unsigned int cpu = raw_smp_processor_id();
const char *strerror = NULL;
@@ -391,6 +203,19 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
panic("BUG()");
}
}
+#endif
+#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
+ /*
+ * Support for the fake instructions, if the instruction fails,
+ * then just execute a illegal opcode failure (like normal).
+ * Don't support these instructions inside the kernel
+ */
+ if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) {
+ if (execute_pseudodbg_assert(fp, opcode))
+ goto traps_done;
+ if (execute_pseudodbg(fp, opcode))
+ goto traps_done;
+ }
#endif
info.si_code = ILL_ILLOPC;
sig = SIGILL;
@@ -672,659 +497,44 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
trace_buffer_restore(j);
}
-/* Typical exception handling routines */
-
-#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
-
-/*
- * Similar to get_user, do some address checking, then dereference
- * Return true on success, false on bad address
- */
-static bool get_instruction(unsigned short *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- /* MMR region will never have instructions */
- if (addr >= SYSMMR_BASE)
- return false;
-
- switch (bfin_mem_access_type(addr, 2)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- *val = *address;
- return true;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy(val, address, 2);
- return true;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy(val, address, 2);
- return true;
- default: /* invalid access */
- return false;
- }
-}
-
-/*
- * decode the instruction if we are printing out the trace, as it
- * makes things easier to follow, without running it through objdump
- * These are the normal instructions which cause change of flow, which
- * would be at the source of the trace buffer
- */
-#if defined(CONFIG_DEBUG_VERBOSE) && defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
-static void decode_instruction(unsigned short *address)
-{
- unsigned short opcode;
-
- if (get_instruction(&opcode, address)) {
- if (opcode == 0x0010)
- verbose_printk("RTS");
- else if (opcode == 0x0011)
- verbose_printk("RTI");
- else if (opcode == 0x0012)
- verbose_printk("RTX");
- else if (opcode == 0x0013)
- verbose_printk("RTN");
- else if (opcode == 0x0014)
- verbose_printk("RTE");
- else if (opcode == 0x0025)
- verbose_printk("EMUEXCPT");
- else if (opcode >= 0x0040 && opcode <= 0x0047)
- verbose_printk("STI R%i", opcode & 7);
- else if (opcode >= 0x0050 && opcode <= 0x0057)
- verbose_printk("JUMP (P%i)", opcode & 7);
- else if (opcode >= 0x0060 && opcode <= 0x0067)
- verbose_printk("CALL (P%i)", opcode & 7);
- else if (opcode >= 0x0070 && opcode <= 0x0077)
- verbose_printk("CALL (PC+P%i)", opcode & 7);
- else if (opcode >= 0x0080 && opcode <= 0x0087)
- verbose_printk("JUMP (PC+P%i)", opcode & 7);
- else if (opcode >= 0x0090 && opcode <= 0x009F)
- verbose_printk("RAISE 0x%x", opcode & 0xF);
- else if (opcode >= 0x00A0 && opcode <= 0x00AF)
- verbose_printk("EXCPT 0x%x", opcode & 0xF);
- else if ((opcode >= 0x1000 && opcode <= 0x13FF) || (opcode >= 0x1800 && opcode <= 0x1BFF))
- verbose_printk("IF !CC JUMP");
- else if ((opcode >= 0x1400 && opcode <= 0x17ff) || (opcode >= 0x1c00 && opcode <= 0x1fff))
- verbose_printk("IF CC JUMP");
- else if (opcode >= 0x2000 && opcode <= 0x2fff)
- verbose_printk("JUMP.S");
- else if (opcode >= 0xe080 && opcode <= 0xe0ff)
- verbose_printk("LSETUP");
- else if (opcode >= 0xe200 && opcode <= 0xe2ff)
- verbose_printk("JUMP.L");
- else if (opcode >= 0xe300 && opcode <= 0xe3ff)
- verbose_printk("CALL pcrel");
- else
- verbose_printk("0x%04x", opcode);
- }
-
-}
-#endif
-
-void dump_bfin_trace_buffer(void)
-{
-#ifdef CONFIG_DEBUG_VERBOSE
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags, i = 0;
- char buf[150];
- unsigned short *addr;
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- int j, index;
-#endif
-
- trace_buffer_save(tflags);
-
- printk(KERN_NOTICE "Hardware Trace:\n");
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- printk(KERN_NOTICE "WARNING: Expanded trace turned on - can not trace exceptions\n");
-#endif
-
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
- decode_address(buf, (unsigned long)bfin_read_TBUF());
- printk(KERN_NOTICE "%4i Target : %s\n", i, buf);
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- printk(KERN_NOTICE " Source : %s ", buf);
- decode_instruction(addr);
- printk("\n");
- }
- }
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- if (trace_buff_offset)
- index = trace_buff_offset / 4;
- else
- index = EXPAND_LEN;
-
- j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
- while (j) {
- decode_address(buf, software_trace_buff[index]);
- printk(KERN_NOTICE "%4i Target : %s\n", i, buf);
- index -= 1;
- if (index < 0 )
- index = EXPAND_LEN;
- decode_address(buf, software_trace_buff[index]);
- printk(KERN_NOTICE " Source : %s ", buf);
- decode_instruction((unsigned short *)software_trace_buff[index]);
- printk("\n");
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- j--;
- i++;
- }
-#endif
-
- trace_buffer_restore(tflags);
-#endif
-#endif
-}
-EXPORT_SYMBOL(dump_bfin_trace_buffer);
-
-#ifdef CONFIG_BUG
-int is_valid_bugaddr(unsigned long addr)
-{
- unsigned short opcode;
-
- if (!get_instruction(&opcode, (unsigned short *)addr))
- return 0;
-
- return opcode == BFIN_BUG_OPCODE;
-}
-#endif
-
-/*
- * Checks to see if the address pointed to is either a
- * 16-bit CALL instruction, or a 32-bit CALL instruction
- */
-static bool is_bfin_call(unsigned short *addr)
-{
- unsigned short opcode = 0, *ins_addr;
- ins_addr = (unsigned short *)addr;
-
- if (!get_instruction(&opcode, ins_addr))
- return false;
-
- if ((opcode >= 0x0060 && opcode <= 0x0067) ||
- (opcode >= 0x0070 && opcode <= 0x0077))
- return true;
-
- ins_addr--;
- if (!get_instruction(&opcode, ins_addr))
- return false;
-
- if (opcode >= 0xE300 && opcode <= 0xE3FF)
- return true;
-
- return false;
-
-}
-
-void show_stack(struct task_struct *task, unsigned long *stack)
-{
-#ifdef CONFIG_PRINTK
- unsigned int *addr, *endstack, *fp = 0, *frame;
- unsigned short *ins_addr;
- char buf[150];
- unsigned int i, j, ret_addr, frame_no = 0;
-
- /*
- * If we have been passed a specific stack, use that one otherwise
- * if we have been passed a task structure, use that, otherwise
- * use the stack of where the variable "stack" exists
- */
-
- if (stack == NULL) {
- if (task) {
- /* We know this is a kernel stack, so this is the start/end */
- stack = (unsigned long *)task->thread.ksp;
- endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
- } else {
- /* print out the existing stack info */
- stack = (unsigned long *)&stack;
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
- }
- } else
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
-
- printk(KERN_NOTICE "Stack info:\n");
- decode_address(buf, (unsigned int)stack);
- printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
-
- if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
- printk(KERN_NOTICE "Invalid stack pointer\n");
- return;
- }
-
- /* First thing is to look for a frame pointer */
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
- if (*addr & 0x1)
- continue;
- ins_addr = (unsigned short *)*addr;
- ins_addr--;
- if (is_bfin_call(ins_addr))
- fp = addr - 1;
-
- if (fp) {
- /* Let's check to see if it is a frame pointer */
- while (fp >= (addr - 1) && fp < endstack
- && fp && ((unsigned int) fp & 0x3) == 0)
- fp = (unsigned int *)*fp;
- if (fp == 0 || fp == endstack) {
- fp = addr - 1;
- break;
- }
- fp = 0;
- }
- }
- if (fp) {
- frame = fp;
- printk(KERN_NOTICE " FP: (0x%p)\n", fp);
- } else
- frame = 0;
-
- /*
- * Now that we think we know where things are, we
- * walk the stack again, this time printing things out
- * incase there is no frame pointer, we still look for
- * valid return addresses
- */
-
- /* First time print out data, next time, print out symbols */
- for (j = 0; j <= 1; j++) {
- if (j)
- printk(KERN_NOTICE "Return addresses in stack:\n");
- else
- printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
-
- fp = frame;
- frame_no = 0;
-
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
- addr < endstack; addr++, i++) {
-
- ret_addr = 0;
- if (!j && i % 8 == 0)
- printk(KERN_NOTICE "%p:",addr);
-
- /* if it is an odd address, or zero, just skip it */
- if (*addr & 0x1 || !*addr)
- goto print;
-
- ins_addr = (unsigned short *)*addr;
-
- /* Go back one instruction, and see if it is a CALL */
- ins_addr--;
- ret_addr = is_bfin_call(ins_addr);
- print:
- if (!j && stack == (unsigned long *)addr)
- printk("[%08x]", *addr);
- else if (ret_addr)
- if (j) {
- decode_address(buf, (unsigned int)*addr);
- if (frame == addr) {
- printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
- continue;
- }
- printk(KERN_NOTICE " address : %s\n", buf);
- } else
- printk("<%08x>", *addr);
- else if (fp == addr) {
- if (j)
- frame = addr+1;
- else
- printk("(%08x)", *addr);
-
- fp = (unsigned int *)*addr;
- frame_no++;
-
- } else if (!j)
- printk(" %08x ", *addr);
- }
- if (!j)
- printk("\n");
- }
-#endif
-}
-EXPORT_SYMBOL(show_stack);
-
-void dump_stack(void)
+asmlinkage void double_fault_c(struct pt_regs *fp)
{
- unsigned long stack;
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags;
+ int j;
+ trace_buffer_save(j);
#endif
- trace_buffer_save(tflags);
- dump_bfin_trace_buffer();
- show_stack(current, &stack);
- trace_buffer_restore(tflags);
-}
-EXPORT_SYMBOL(dump_stack);
-void dump_bfin_process(struct pt_regs *fp)
-{
+ console_verbose();
+ oops_in_progress = 1;
#ifdef CONFIG_DEBUG_VERBOSE
- /* We should be able to look at fp->ipend, but we don't push it on the
- * stack all the time, so do this until we fix that */
- unsigned int context = bfin_read_IPEND();
-
- if (oops_in_progress)
- verbose_printk(KERN_EMERG "Kernel OOPS in progress\n");
-
- if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
- verbose_printk(KERN_NOTICE "HW Error context\n");
- else if (context & 0x0020)
- verbose_printk(KERN_NOTICE "Deferred Exception context\n");
- else if (context & 0x3FC0)
- verbose_printk(KERN_NOTICE "Interrupt context\n");
- else if (context & 0x4000)
- verbose_printk(KERN_NOTICE "Deferred Interrupt context\n");
- else if (context & 0x8000)
- verbose_printk(KERN_NOTICE "Kernel process context\n");
-
- /* Because we are crashing, and pointers could be bad, we check things
- * pretty closely before we use them
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3) && current->pid) {
- verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n");
- if (current->comm >= (char *)FIXED_CODE_START)
- verbose_printk(KERN_NOTICE "COMM=%s PID=%d",
- current->comm, current->pid);
- else
- verbose_printk(KERN_NOTICE "COMM= invalid");
+ printk(KERN_EMERG "Double Fault\n");
+#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
+ if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
+ unsigned int cpu = raw_smp_processor_id();
+ char buf[150];
+ decode_address(buf, cpu_pda[cpu].retx_doublefault);
+ printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
+ (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
+ decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
+ printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
+ decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
+ printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
- printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu);
- if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START)
- verbose_printk(KERN_NOTICE
- "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
- " BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
- (void *)current->mm->start_code,
- (void *)current->mm->end_code,
- (void *)current->mm->start_data,
- (void *)current->mm->end_data,
- (void *)current->mm->end_data,
- (void *)current->mm->brk,
- (void *)current->mm->start_stack);
- else
- verbose_printk(KERN_NOTICE "invalid mm\n");
+ decode_address(buf, fp->retx);
+ printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
} else
- verbose_printk(KERN_NOTICE
- "No Valid process in current context\n");
-#endif
-}
-
-void dump_bfin_mem(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_VERBOSE
- unsigned short *addr, *erraddr, val = 0, err = 0;
- char sti = 0, buf[6];
-
- erraddr = (void *)fp->pc;
-
- verbose_printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr);
-
- for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
- addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
- addr++) {
- if (!((unsigned long)addr & 0xF))
- verbose_printk(KERN_NOTICE "0x%p: ", addr);
-
- if (!get_instruction(&val, addr)) {
- val = 0;
- sprintf(buf, "????");
- } else
- sprintf(buf, "%04x", val);
-
- if (addr == erraddr) {
- verbose_printk("[%s]", buf);
- err = val;
- } else
- verbose_printk(" %s ", buf);
-
- /* Do any previous instructions turn on interrupts? */
- if (addr <= erraddr && /* in the past */
- ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
- val == 0x017b)) /* [SP++] = RETI */
- sti = 1;
- }
-
- verbose_printk("\n");
-
- /* Hardware error interrupts can be deferred */
- if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
- oops_in_progress)){
- verbose_printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n");
-#ifndef CONFIG_DEBUG_HWERR
- verbose_printk(KERN_NOTICE
-"The remaining message may be meaningless\n"
-"You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
-#else
- /* If we are handling only one peripheral interrupt
- * and current mm and pid are valid, and the last error
- * was in that user space process's text area
- * print it out - because that is where the problem exists
- */
- if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
- (current->pid && current->mm)) {
- /* And the last RETI points to the current userspace context */
- if ((fp + 1)->pc >= current->mm->start_code &&
- (fp + 1)->pc <= current->mm->end_code) {
- verbose_printk(KERN_NOTICE "It might be better to look around here :\n");
- verbose_printk(KERN_NOTICE "-------------------------------------------\n");
- show_regs(fp + 1);
- verbose_printk(KERN_NOTICE "-------------------------------------------\n");
- }
- }
-#endif
- }
-#endif
-}
-
-void show_regs(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_VERBOSE
- char buf [150];
- struct irqaction *action;
- unsigned int i;
- unsigned long flags = 0;
- unsigned int cpu = raw_smp_processor_id();
- unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
-
- verbose_printk(KERN_NOTICE "\n");
- if (CPUID != bfin_cpuid())
- verbose_printk(KERN_NOTICE "Compiled for cpu family 0x%04x (Rev %d), "
- "but running on:0x%04x (Rev %d)\n",
- CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
-
- verbose_printk(KERN_NOTICE "ADSP-%s-0.%d",
- CPU, bfin_compiled_revid());
-
- if (bfin_compiled_revid() != bfin_revid())
- verbose_printk("(Detected 0.%d)", bfin_revid());
-
- verbose_printk(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
- get_cclk()/1000000, get_sclk()/1000000,
-#ifdef CONFIG_MPU
- "mpu on"
-#else
- "mpu off"
-#endif
- );
-
- verbose_printk(KERN_NOTICE "%s", linux_banner);
-
- verbose_printk(KERN_NOTICE "\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
- verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
- (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
- if (fp->ipend & EVT_IRPTEN)
- verbose_printk(KERN_NOTICE " Global Interrupts Disabled (IPEND[4])\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
- EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
- verbose_printk(KERN_NOTICE " Peripheral interrupts masked off\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
- verbose_printk(KERN_NOTICE " Kernel interrupts masked off\n");
- if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
- verbose_printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n",
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
-#ifdef EBIU_ERRMST
- /* If the error was from the EBIU, print it out */
- if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
- verbose_printk(KERN_NOTICE " EBIU Error Reason : 0x%04x\n",
- bfin_read_EBIU_ERRMST());
- verbose_printk(KERN_NOTICE " EBIU Error Address : 0x%08x\n",
- bfin_read_EBIU_ERRADD());
- }
#endif
+ {
+ dump_bfin_process(fp);
+ dump_bfin_mem(fp);
+ show_regs(fp);
+ dump_bfin_trace_buffer();
}
- verbose_printk(KERN_NOTICE " EXCAUSE : 0x%lx\n",
- fp->seqstat & SEQSTAT_EXCAUSE);
- for (i = 2; i <= 15 ; i++) {
- if (fp->ipend & (1 << i)) {
- if (i != 4) {
- decode_address(buf, bfin_read32(EVT0 + 4*i));
- verbose_printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf);
- } else
- verbose_printk(KERN_NOTICE " interrupts disabled\n");
- }
- }
-
- /* if no interrupts are going off, don't print this out */
- if (fp->ipend & ~0x3F) {
- for (i = 0; i < (NR_IRQS - 1); i++) {
- if (!in_atomic)
- raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-
- action = irq_desc[i].action;
- if (!action)
- goto unlock;
-
- decode_address(buf, (unsigned int)action->handler);
- verbose_printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf);
- for (action = action->next; action; action = action->next) {
- decode_address(buf, (unsigned int)action->handler);
- verbose_printk(", %s", buf);
- }
- verbose_printk("\n");
-unlock:
- if (!in_atomic)
- raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
- }
- }
-
- decode_address(buf, fp->rete);
- verbose_printk(KERN_NOTICE " RETE: %s\n", buf);
- decode_address(buf, fp->retn);
- verbose_printk(KERN_NOTICE " RETN: %s\n", buf);
- decode_address(buf, fp->retx);
- verbose_printk(KERN_NOTICE " RETX: %s\n", buf);
- decode_address(buf, fp->rets);
- verbose_printk(KERN_NOTICE " RETS: %s\n", buf);
- decode_address(buf, fp->pc);
- verbose_printk(KERN_NOTICE " PC : %s\n", buf);
-
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
- (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
- decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
- verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf);
- }
-
- verbose_printk(KERN_NOTICE "PROCESSOR STATE:\n");
- verbose_printk(KERN_NOTICE " R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- verbose_printk(KERN_NOTICE " R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- verbose_printk(KERN_NOTICE " P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- verbose_printk(KERN_NOTICE " P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
- fp->p4, fp->p5, fp->fp, (long)fp);
- verbose_printk(KERN_NOTICE " LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- verbose_printk(KERN_NOTICE " LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- verbose_printk(KERN_NOTICE " B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- verbose_printk(KERN_NOTICE " B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- verbose_printk(KERN_NOTICE " B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- verbose_printk(KERN_NOTICE " B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
- verbose_printk(KERN_NOTICE "A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- verbose_printk(KERN_NOTICE "USP : %08lx ASTAT: %08lx\n",
- rdusp(), fp->astat);
-
- verbose_printk(KERN_NOTICE "\n");
#endif
-}
-
-#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
-asmlinkage int sys_bfin_spinlock(int *spinlock)__attribute__((l1_text));
-#endif
-
-static DEFINE_SPINLOCK(bfin_spinlock_lock);
-
-asmlinkage int sys_bfin_spinlock(int *p)
-{
- int ret, tmp = 0;
-
- spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
- ret = get_user(tmp, p);
- if (likely(ret == 0)) {
- if (unlikely(tmp))
- ret = 1;
- else
- put_user(1, p);
- }
- spin_unlock(&bfin_spinlock_lock);
- return ret;
-}
-
-int bfin_request_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != ex_replaceable)
- return -EBUSY;
-
- ex_table[exception] = handler;
+ panic("Double Fault - unrecoverable event");
- return 0;
}
-EXPORT_SYMBOL(bfin_request_exception);
-
-int bfin_free_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
- if (curr_handler != handler)
- return -EBUSY;
-
- ex_table[exception] = ex_replaceable;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_free_exception);
void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
{
@@ -1349,3 +559,23 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
dump_stack();
panic("Unrecoverable event");
}
+
+#ifdef CONFIG_BUG
+int is_valid_bugaddr(unsigned long addr)
+{
+ unsigned int opcode;
+
+ if (!get_instruction(&opcode, (unsigned short *)addr))
+ return 0;
+
+ return opcode == BFIN_BUG_OPCODE;
+}
+#endif
+
+/* stub this out */
+#ifndef CONFIG_DEBUG_VERBOSE
+void show_regs(struct pt_regs *fp)
+{
+
+}
+#endif
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
index c30d99b109694bcee489a51acc808288a38f7b2b..eab1bef3f5bf37100c07a5d2de9868e2bc352004 100644
--- a/arch/blackfin/lib/memset.S
+++ b/arch/blackfin/lib/memset.S
@@ -20,6 +20,7 @@
* R1 = filler byte
* R2 = count
* Favours word aligned data.
+ * The strncpy assumes that I0 and I1 are not used in this function
*/
ENTRY(_memset)
diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S
new file mode 100644
index 0000000000000000000000000000000000000000..d7c1d158973bd6684f31aa557f4a907a45ccc27b
--- /dev/null
+++ b/arch/blackfin/lib/strcmp.S
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
+ */
+
+#include <linux/linkage.h>
+
+/* void *strcmp(char *s1, const char *s2);
+ * R0 = address (s1)
+ * R1 = address (s2)
+ *
+ * Returns an integer less than, equal to, or greater than zero if s1
+ * (or the first n bytes thereof) is found, respectively, to be less
+ * than, to match, or be greater than s2.
+ */
+
+#ifdef CONFIG_STRCMP_L1
+.section .l1.text
+#else
+.text
+#endif
+
+.align 2
+
+ENTRY(_strcmp)
+ P0 = R0 ; /* s1 */
+ P1 = R1 ; /* s2 */
+
+1:
+ R0 = B[P0++] (Z); /* get *s1 */
+ R1 = B[P1++] (Z); /* get *s2 */
+ CC = R0 == R1; /* compare a byte */
+ if ! cc jump 2f; /* not equal, break out */
+ CC = R0; /* at end of s1? */
+ if cc jump 1b (bp); /* no, keep going */
+ jump.s 3f; /* strings are equal */
+2:
+ R0 = R0 - R1; /* *s1 - *s2 */
+3:
+ RTS;
+
+ENDPROC(_strcmp)
diff --git a/arch/blackfin/lib/strcmp.c b/arch/blackfin/lib/strcmp.c
deleted file mode 100644
index fde39a1950ce8903124831d8758692cad384f648..0000000000000000000000000000000000000000
--- a/arch/blackfin/lib/strcmp.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Provide symbol in case str func is not inlined.
- *
- * Copyright (c) 2006-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define strcmp __inline_strcmp
-#include <asm/string.h>
-#undef strcmp
-
-#include <linux/module.h>
-
-int strcmp(const char *dest, const char *src)
-{
- return __inline_strcmp(dest, src);
-}
-EXPORT_SYMBOL(strcmp);
diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S
new file mode 100644
index 0000000000000000000000000000000000000000..a6a0c63638066ede9095adda1cbb25bbae1f10f2
--- /dev/null
+++ b/arch/blackfin/lib/strcpy.S
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
+ */
+
+#include <linux/linkage.h>
+
+/* void *strcpy(char *dest, const char *src);
+ * R0 = address (dest)
+ * R1 = address (src)
+ *
+ * Returns a pointer to the destination string dest
+ */
+
+#ifdef CONFIG_STRCPY_L1
+.section .l1.text
+#else
+.text
+#endif
+
+.align 2
+
+ENTRY(_strcpy)
+ P0 = R0 ; /* dst*/
+ P1 = R1 ; /* src*/
+
+1:
+ R1 = B [P1++] (Z);
+ B [P0++] = R1;
+ CC = R1;
+ if cc jump 1b (bp);
+ RTS;
+
+ENDPROC(_strcpy)
diff --git a/arch/blackfin/lib/strcpy.c b/arch/blackfin/lib/strcpy.c
deleted file mode 100644
index 2a8836b1f4d37abf3700693d39f8cccbf93c2fe7..0000000000000000000000000000000000000000
--- a/arch/blackfin/lib/strcpy.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Provide symbol in case str func is not inlined.
- *
- * Copyright (c) 2006-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define strcpy __inline_strcpy
-#include <asm/string.h>
-#undef strcpy
-
-#include <linux/module.h>
-
-char *strcpy(char *dest, const char *src)
-{
- return __inline_strcpy(dest, src);
-}
-EXPORT_SYMBOL(strcpy);
diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S
new file mode 100644
index 0000000000000000000000000000000000000000..6da37c34a847def6f37d9eb9becef3aa1b130430
--- /dev/null
+++ b/arch/blackfin/lib/strncmp.S
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
+ */
+
+#include <linux/linkage.h>
+
+/* void *strncpy(char *s1, const char *s2, size_t n);
+ * R0 = address (dest)
+ * R1 = address (src)
+ * R2 = size (n)
+ * Returns a pointer to the destination string dest
+ */
+
+#ifdef CONFIG_STRNCMP_L1
+.section .l1.text
+#else
+.text
+#endif
+
+.align 2
+
+ENTRY(_strncmp)
+ CC = R2 == 0;
+ if CC JUMP 5f;
+
+ P0 = R0 ; /* s1 */
+ P1 = R1 ; /* s2 */
+1:
+ R0 = B[P0++] (Z); /* get *s1 */
+ R1 = B[P1++] (Z); /* get *s2 */
+ CC = R0 == R1; /* compare a byte */
+ if ! cc jump 3f; /* not equal, break out */
+ CC = R0; /* at end of s1? */
+ if ! cc jump 4f; /* yes, all done */
+ R2 += -1; /* no, adjust count */
+ CC = R2 == 0;
+ if ! cc jump 1b (bp); /* more to do, keep going */
+2:
+ R0 = 0; /* strings are equal */
+ jump.s 4f;
+3:
+ R0 = R0 - R1; /* *s1 - *s2 */
+4:
+ RTS;
+
+5:
+ R0 = 0;
+ RTS;
+
+ENDPROC(_strncmp)
diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c
deleted file mode 100644
index 46518b1d29831bae0184daa34b2b45889563448f..0000000000000000000000000000000000000000
--- a/arch/blackfin/lib/strncmp.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Provide symbol in case str func is not inlined.
- *
- * Copyright (c) 2006-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define strncmp __inline_strncmp
-#include <asm/string.h>
-#include <linux/module.h>
-#undef strncmp
-
-int strncmp(const char *cs, const char *ct, size_t count)
-{
- return __inline_strncmp(cs, ct, count);
-}
-EXPORT_SYMBOL(strncmp);
diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S
new file mode 100644
index 0000000000000000000000000000000000000000..f3931d50b4a715a50878363a43bd14e9c63b9dd1
--- /dev/null
+++ b/arch/blackfin/lib/strncpy.S
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
+ */
+
+#include <linux/linkage.h>
+#include <asm/context.S>
+
+/* void *strncpy(char *dest, const char *src, size_t n);
+ * R0 = address (dest)
+ * R1 = address (src)
+ * R2 = size
+ * Returns a pointer (R0) to the destination string dest
+ * we do this by not changing R0
+ */
+
+#ifdef CONFIG_STRNCPY_L1
+.section .l1.text
+#else
+.text
+#endif
+
+.align 2
+
+ENTRY(_strncpy)
+ CC = R2 == 0;
+ if CC JUMP 4f;
+
+ P2 = R2 ; /* size */
+ P0 = R0 ; /* dst*/
+ P1 = R1 ; /* src*/
+
+ LSETUP (1f, 2f) LC0 = P2;
+1:
+ R1 = B [P1++] (Z);
+ B [P0++] = R1;
+ CC = R1 == 0;
+2:
+ if CC jump 3f;
+
+ RTS;
+
+ /* if src is shorter than n, we need to null pad bytes in dest
+ * but, we can get here when the last byte is zero, and we don't
+ * want to copy an extra byte at the end, so we need to check
+ */
+3:
+ R2 = LC0;
+ CC = R2
+ if ! CC jump 6f;
+
+ /* if the required null padded portion is small, do it here, rather than
+ * handling the overhead of memset (which is OK when things are big).
+ */
+ R3 = 0x20;
+ CC = R2 < R3;
+ IF CC jump 4f;
+
+ R2 += -1;
+
+ /* Set things up for memset
+ * R0 = address
+ * R1 = filler byte (this case it's zero, set above)
+ * R2 = count (set above)
+ */
+
+ I1 = R0;
+ R0 = RETS;
+ I0 = R0;
+ R0 = P0;
+ pseudo_long_call _memset, p0;
+ R0 = I0;
+ RETS = R0;
+ R0 = I1;
+ RTS;
+
+4:
+ LSETUP(5f, 5f) LC0;
+5:
+ B [P0++] = R1;
+6:
+ RTS;
+
+ENDPROC(_strncpy)
diff --git a/arch/blackfin/lib/strncpy.c b/arch/blackfin/lib/strncpy.c
deleted file mode 100644
index ea1dc6bf2373c7a6a3485706ef11c47f07a2fcc5..0000000000000000000000000000000000000000
--- a/arch/blackfin/lib/strncpy.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Provide symbol in case str func is not inlined.
- *
- * Copyright (c) 2006-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define strncpy __inline_strncpy
-#include <asm/string.h>
-#undef strncpy
-
-#include <linux/module.h>
-
-char *strncpy(char *dest, const char *src, size_t n)
-{
- return __inline_strncpy(dest, src, n);
-}
-EXPORT_SYMBOL(strncpy);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index ebe76d1e874aabbb183bf6fe43dd948c1360431b..f392af641657d78f5be0294cc162c4c294c4f5d2 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -98,6 +98,10 @@ static struct musb_hdrc_config musb_config = {
.num_eps = 8,
.dma_channels = 8,
.gpio_vrsel = GPIO_PF11,
+ /* Some custom boards need to be active low, just set it to "0"
+ * if it is the case.
+ */
+ .gpio_vrsel_active = 1,
};
static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 55069af4f67dd88b69230c659e67c8b821713de0..606eb36b9d6ea2ce31d9d9082d0c8de9ac5512d4 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -62,6 +62,10 @@ static struct musb_hdrc_config musb_config = {
.num_eps = 8,
.dma_channels = 8,
.gpio_vrsel = GPIO_PG13,
+ /* Some custom boards need to be active low, just set it to "0"
+ * if it is the case.
+ */
+ .gpio_vrsel_active = 1,
};
static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 923383386aa18cee70cd86efb4db19fe5017e8a1..a05c967a24cfc22046fde2709da087a6c30bfef1 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -102,6 +102,10 @@ static struct musb_hdrc_config musb_config = {
.num_eps = 8,
.dma_channels = 8,
.gpio_vrsel = GPIO_PG13,
+ /* Some custom boards need to be active low, just set it to "0"
+ * if it is the case.
+ */
+ .gpio_vrsel_active = 1,
};
static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index c489d602c59013036d1bb0b546fd208d6773091a..05d45994480eaf8b2dae60ae59aeb439b2ebb05b 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -23,12 +23,13 @@
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
+#include <asm/portmux.h>
#include <linux/spi/ad7877.h>
/*
* Name the Board for the /proc/cpuinfo
*/
-char *bfin_board_name = "CamSig Minotaur BF537";
+const char bfin_board_name[] = "CamSig Minotaur BF537";
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
static struct resource bfin_pcmcia_cf_resources[] = {
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 066d5c261f47e3a34def90192dadc06c582de7ed..cf396ea40092a010344554f469a418160b37a1e0 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1702,628 +1702,6 @@
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
-/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
-/* CAN_CONTROL Masks */
-#define SRS 0x0001 /* Software Reset */
-#define DNM 0x0002 /* Device Net Mode */
-#define ABO 0x0004 /* Auto-Bus On Enable */
-#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
-#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
-#define SMR 0x0020 /* Sleep Mode Request */
-#define CSR 0x0040 /* CAN Suspend Mode Request */
-#define CCR 0x0080 /* CAN Configuration Mode Request */
-
-/* CAN_STATUS Masks */
-#define WT 0x0001 /* TX Warning Flag */
-#define WR 0x0002 /* RX Warning Flag */
-#define EP 0x0004 /* Error Passive Mode */
-#define EBO 0x0008 /* Error Bus Off Mode */
-#define SMA 0x0020 /* Sleep Mode Acknowledge */
-#define CSA 0x0040 /* Suspend Mode Acknowledge */
-#define CCA 0x0080 /* Configuration Mode Acknowledge */
-#define MBPTR 0x1F00 /* Mailbox Pointer */
-#define TRM 0x4000 /* Transmit Mode */
-#define REC 0x8000 /* Receive Mode */
-
-/* CAN_CLOCK Masks */
-#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
-
-/* CAN_TIMING Masks */
-#define TSEG1 0x000F /* Time Segment 1 */
-#define TSEG2 0x0070 /* Time Segment 2 */
-#define SAM 0x0080 /* Sampling */
-#define SJW 0x0300 /* Synchronization Jump Width */
-
-/* CAN_DEBUG Masks */
-#define DEC 0x0001 /* Disable CAN Error Counters */
-#define DRI 0x0002 /* Disable CAN RX Input */
-#define DTO 0x0004 /* Disable CAN TX Output */
-#define DIL 0x0008 /* Disable CAN Internal Loop */
-#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
-#define MRB 0x0020 /* Mode Read Back Enable */
-#define CDE 0x8000 /* CAN Debug Enable */
-
-/* CAN_CEC Masks */
-#define RXECNT 0x00FF /* Receive Error Counter */
-#define TXECNT 0xFF00 /* Transmit Error Counter */
-
-/* CAN_INTR Masks */
-#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
-#define MBRIF MBRIRQ /* legacy */
-#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
-#define MBTIF MBTIRQ /* legacy */
-#define GIRQ 0x0004 /* Global Interrupt */
-#define SMACK 0x0008 /* Sleep Mode Acknowledge */
-#define CANTX 0x0040 /* CAN TX Bus Value */
-#define CANRX 0x0080 /* CAN RX Bus Value */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
-#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define IDE 0x2000 /* Identifier Extension */
-#define RTR 0x4000 /* Remote Frame Transmission Request */
-#define AME 0x8000 /* Acceptance Mask Enable */
-
-/* CAN_MBxx_TIMESTAMP Masks */
-#define TSV 0xFFFF /* Timestamp */
-
-/* CAN_MBxx_LENGTH Masks */
-#define DLC 0x000F /* Data Length Code */
-
-/* CAN_AMxxH and CAN_AMxxL Masks */
-#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
-#define FMD 0x4000 /* Full Mask Data Field Enable */
-#define FDF 0x8000 /* Filter On Data Field Enable */
-
-/* CAN_MC1 Masks */
-#define MC0 0x0001 /* Enable Mailbox 0 */
-#define MC1 0x0002 /* Enable Mailbox 1 */
-#define MC2 0x0004 /* Enable Mailbox 2 */
-#define MC3 0x0008 /* Enable Mailbox 3 */
-#define MC4 0x0010 /* Enable Mailbox 4 */
-#define MC5 0x0020 /* Enable Mailbox 5 */
-#define MC6 0x0040 /* Enable Mailbox 6 */
-#define MC7 0x0080 /* Enable Mailbox 7 */
-#define MC8 0x0100 /* Enable Mailbox 8 */
-#define MC9 0x0200 /* Enable Mailbox 9 */
-#define MC10 0x0400 /* Enable Mailbox 10 */
-#define MC11 0x0800 /* Enable Mailbox 11 */
-#define MC12 0x1000 /* Enable Mailbox 12 */
-#define MC13 0x2000 /* Enable Mailbox 13 */
-#define MC14 0x4000 /* Enable Mailbox 14 */
-#define MC15 0x8000 /* Enable Mailbox 15 */
-
-/* CAN_MC2 Masks */
-#define MC16 0x0001 /* Enable Mailbox 16 */
-#define MC17 0x0002 /* Enable Mailbox 17 */
-#define MC18 0x0004 /* Enable Mailbox 18 */
-#define MC19 0x0008 /* Enable Mailbox 19 */
-#define MC20 0x0010 /* Enable Mailbox 20 */
-#define MC21 0x0020 /* Enable Mailbox 21 */
-#define MC22 0x0040 /* Enable Mailbox 22 */
-#define MC23 0x0080 /* Enable Mailbox 23 */
-#define MC24 0x0100 /* Enable Mailbox 24 */
-#define MC25 0x0200 /* Enable Mailbox 25 */
-#define MC26 0x0400 /* Enable Mailbox 26 */
-#define MC27 0x0800 /* Enable Mailbox 27 */
-#define MC28 0x1000 /* Enable Mailbox 28 */
-#define MC29 0x2000 /* Enable Mailbox 29 */
-#define MC30 0x4000 /* Enable Mailbox 30 */
-#define MC31 0x8000 /* Enable Mailbox 31 */
-
-/* CAN_MD1 Masks */
-#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
-#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
-#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
-#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
-#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
-#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
-#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
-#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
-#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
-#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
-#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
-#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
-#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
-#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
-#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
-#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
-
-/* CAN_MD2 Masks */
-#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
-#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
-#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
-#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
-#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
-#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
-#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
-#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
-#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
-#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
-#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
-#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
-#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
-#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
-#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
-#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
-
-/* CAN_RMP1 Masks */
-#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
-#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
-#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
-#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
-#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
-#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
-#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
-#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
-#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
-#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
-#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
-#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
-#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
-#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
-#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
-#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
-
-/* CAN_RMP2 Masks */
-#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
-#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
-#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
-#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
-#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
-#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
-#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
-#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
-#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
-#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
-#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
-#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
-#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
-#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
-#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
-#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
-
-/* CAN_RML1 Masks */
-#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
-#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
-#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
-#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
-#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
-#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
-#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
-#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
-#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
-#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
-#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
-#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
-#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
-#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
-#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
-#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
-
-/* CAN_RML2 Masks */
-#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
-#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
-#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
-#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
-#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
-#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
-#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
-#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
-#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
-#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
-#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
-#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
-#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
-#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
-#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
-#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
-
-/* CAN_OPSS1 Masks */
-#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
-#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
-#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
-#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
-#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
-#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
-#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
-#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
-#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
-#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
-#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
-#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
-#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
-#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
-#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
-#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
-
-/* CAN_OPSS2 Masks */
-#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
-#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
-#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
-#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
-#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
-#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
-#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
-#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
-#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
-#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
-#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
-#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
-#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
-#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
-#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
-#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
-
-/* CAN_TRR1 Masks */
-#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
-#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
-#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
-#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
-#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
-#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
-#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
-#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
-#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
-#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
-#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
-#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
-#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
-#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
-#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
-#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
-
-/* CAN_TRR2 Masks */
-#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
-#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
-#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
-#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
-#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
-#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
-#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
-#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
-#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
-#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
-#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
-#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
-#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
-#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
-#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
-#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
-
-/* CAN_TRS1 Masks */
-#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
-#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
-#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
-#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
-#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
-#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
-#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
-#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
-#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
-#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
-#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
-#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
-#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
-#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
-#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
-#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
-
-/* CAN_TRS2 Masks */
-#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
-#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
-#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
-#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
-#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
-#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
-#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
-#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
-#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
-#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
-#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
-#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
-#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
-#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
-#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
-#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
-
-/* CAN_AA1 Masks */
-#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
-#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
-#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
-#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
-#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
-#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
-#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
-#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
-#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
-#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
-#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
-#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
-#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
-#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
-#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
-#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
-
-/* CAN_AA2 Masks */
-#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
-#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
-#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
-#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
-#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
-#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
-#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
-#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
-#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
-#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
-#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
-#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
-#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
-#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
-#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
-#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
-
-/* CAN_TA1 Masks */
-#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
-#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
-#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
-#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
-#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
-#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
-#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
-#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
-#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
-#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
-#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
-#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
-#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
-#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
-#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
-#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
-
-/* CAN_TA2 Masks */
-#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
-#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
-#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
-#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
-#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
-#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
-#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
-#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
-#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
-#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
-#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
-#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
-#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
-#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
-#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
-#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
-
-/* CAN_MBTD Masks */
-#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
-#define TDA 0x0040 /* Temporary Disable Acknowledge */
-#define TDR 0x0080 /* Temporary Disable Request */
-
-/* CAN_RFH1 Masks */
-#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
-#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
-#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
-#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
-#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
-#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
-#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
-#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
-#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
-#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
-#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
-#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
-#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
-#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
-#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
-#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
-
-/* CAN_RFH2 Masks */
-#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
-#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
-#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
-#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
-#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
-#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
-#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
-#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
-#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
-#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
-#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
-#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
-#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
-#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
-#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
-#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
-
-/* CAN_MBTIF1 Masks */
-#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
-#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
-#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
-#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
-#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
-#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
-#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
-#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
-#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
-#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
-#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
-#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
-#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
-#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
-#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
-#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBTIF2 Masks */
-#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
-#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
-#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
-#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
-#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
-#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
-#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
-#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
-#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
-#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
-#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
-#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
-#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
-#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
-#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
-#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBRIF1 Masks */
-#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
-#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
-#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
-#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
-#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
-#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
-#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
-#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
-#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
-#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
-#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
-#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
-#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
-#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
-#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
-#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBRIF2 Masks */
-#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
-#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
-#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
-#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
-#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
-#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
-#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
-#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
-#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
-#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
-#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
-#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
-#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
-#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
-#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
-#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBIM1 Masks */
-#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
-#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
-#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
-#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
-#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
-#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
-#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
-#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
-#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
-#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
-#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
-#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
-#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
-#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
-#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
-#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
-
-/* CAN_MBIM2 Masks */
-#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
-#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
-#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
-#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
-#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
-#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
-#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
-#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
-#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
-#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
-#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
-#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
-#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
-#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
-#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
-#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
-
-/* CAN_GIM Masks */
-#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
-#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
-#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
-#define BOIM 0x0008 /* Enable Bus Off Interrupt */
-#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
-#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
-#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
-#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
-#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
-#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
-#define ADIM 0x0400 /* Enable Access Denied Interrupt */
-
-/* CAN_GIS Masks */
-#define EWTIS 0x0001 /* TX Error Count IRQ Status */
-#define EWRIS 0x0002 /* RX Error Count IRQ Status */
-#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
-#define BOIS 0x0008 /* Bus Off IRQ Status */
-#define WUIS 0x0010 /* Wake-Up IRQ Status */
-#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
-#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
-#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
-#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
-#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
-#define ADIS 0x0400 /* Access Denied IRQ Status */
-
-/* CAN_GIF Masks */
-#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
-#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
-#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
-#define BOIF 0x0008 /* Bus Off IRQ Flag */
-#define WUIF 0x0010 /* Wake-Up IRQ Flag */
-#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
-#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
-#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
-#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
-#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
-#define ADIF 0x0400 /* Access Denied IRQ Flag */
-
-/* CAN_UCCNF Masks */
-#define UCCNF 0x000F /* Universal Counter Mode */
-#define UC_STAMP 0x0001 /* Timestamp Mode */
-#define UC_WDOG 0x0002 /* Watchdog Mode */
-#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
-#define UC_ERROR 0x0006 /* CAN Error Frame Count */
-#define UC_OVER 0x0007 /* CAN Overload Frame Count */
-#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
-#define UC_AA 0x0009 /* TX Abort Count */
-#define UC_TA 0x000A /* TX Successful Count */
-#define UC_REJECT 0x000B /* RX Message Rejected Count */
-#define UC_RML 0x000C /* RX Message Lost Count */
-#define UC_RX 0x000D /* Total Successful RX Messages Count */
-#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
-#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
-#define UCRC 0x0020 /* Universal Counter Reload/Clear */
-#define UCCT 0x0040 /* Universal Counter CAN Trigger */
-#define UCE 0x0080 /* Universal Counter Enable */
-
-/* CAN_ESR Masks */
-#define ACKE 0x0004 /* Acknowledge Error */
-#define SER 0x0008 /* Stuff Error */
-#define CRCE 0x0010 /* CRC Error */
-#define SA0 0x0020 /* Stuck At Dominant Error */
-#define BEF 0x0040 /* Bit Error Flag */
-#define FER 0x0080 /* Form Error Flag */
-
-/* CAN_EWR Masks */
-#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
-#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
-
/* ******************* PIN CONTROL REGISTER MASKS ************************/
/* PORT_MUX Masks */
#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 789a4f226f7b2c8b0b75eb763e12b693830978c9..1a6d617c5fcf8680597f0b5b4143be15b5590201 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -74,7 +74,7 @@
#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
-#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */
+#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */
#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index fac563e6f62f7adbe357cab7d501d1c6fc276ac9..d7061d9f2a832cd2c0936edf06db800d03a62637 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -2418,625 +2418,4 @@
#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
-
-/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
-/* CAN_CONTROL Masks */
-#define SRS 0x0001 /* Software Reset */
-#define DNM 0x0002 /* Device Net Mode */
-#define ABO 0x0004 /* Auto-Bus On Enable */
-#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
-#define SMR 0x0020 /* Sleep Mode Request */
-#define CSR 0x0040 /* CAN Suspend Mode Request */
-#define CCR 0x0080 /* CAN Configuration Mode Request */
-
-/* CAN_STATUS Masks */
-#define WT 0x0001 /* TX Warning Flag */
-#define WR 0x0002 /* RX Warning Flag */
-#define EP 0x0004 /* Error Passive Mode */
-#define EBO 0x0008 /* Error Bus Off Mode */
-#define CSA 0x0040 /* Suspend Mode Acknowledge */
-#define CCA 0x0080 /* Configuration Mode Acknowledge */
-#define MBPTR 0x1F00 /* Mailbox Pointer */
-#define TRM 0x4000 /* Transmit Mode */
-#define REC 0x8000 /* Receive Mode */
-
-/* CAN_CLOCK Masks */
-#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
-
-/* CAN_TIMING Masks */
-#define TSEG1 0x000F /* Time Segment 1 */
-#define TSEG2 0x0070 /* Time Segment 2 */
-#define SAM 0x0080 /* Sampling */
-#define SJW 0x0300 /* Synchronization Jump Width */
-
-/* CAN_DEBUG Masks */
-#define DEC 0x0001 /* Disable CAN Error Counters */
-#define DRI 0x0002 /* Disable CAN RX Input */
-#define DTO 0x0004 /* Disable CAN TX Output */
-#define DIL 0x0008 /* Disable CAN Internal Loop */
-#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
-#define MRB 0x0020 /* Mode Read Back Enable */
-#define CDE 0x8000 /* CAN Debug Enable */
-
-/* CAN_CEC Masks */
-#define RXECNT 0x00FF /* Receive Error Counter */
-#define TXECNT 0xFF00 /* Transmit Error Counter */
-
-/* CAN_INTR Masks */
-#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
-#define MBRIF MBRIRQ /* legacy */
-#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
-#define MBTIF MBTIRQ /* legacy */
-#define GIRQ 0x0004 /* Global Interrupt */
-#define SMACK 0x0008 /* Sleep Mode Acknowledge */
-#define CANTX 0x0040 /* CAN TX Bus Value */
-#define CANRX 0x0080 /* CAN RX Bus Value */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
-#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define IDE 0x2000 /* Identifier Extension */
-#define RTR 0x4000 /* Remote Frame Transmission Request */
-#define AME 0x8000 /* Acceptance Mask Enable */
-
-/* CAN_MBxx_TIMESTAMP Masks */
-#define TSV 0xFFFF /* Timestamp */
-
-/* CAN_MBxx_LENGTH Masks */
-#define DLC 0x000F /* Data Length Code */
-
-/* CAN_AMxxH and CAN_AMxxL Masks */
-#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
-#define FMD 0x4000 /* Full Mask Data Field Enable */
-#define FDF 0x8000 /* Filter On Data Field Enable */
-
-/* CAN_MC1 Masks */
-#define MC0 0x0001 /* Enable Mailbox 0 */
-#define MC1 0x0002 /* Enable Mailbox 1 */
-#define MC2 0x0004 /* Enable Mailbox 2 */
-#define MC3 0x0008 /* Enable Mailbox 3 */
-#define MC4 0x0010 /* Enable Mailbox 4 */
-#define MC5 0x0020 /* Enable Mailbox 5 */
-#define MC6 0x0040 /* Enable Mailbox 6 */
-#define MC7 0x0080 /* Enable Mailbox 7 */
-#define MC8 0x0100 /* Enable Mailbox 8 */
-#define MC9 0x0200 /* Enable Mailbox 9 */
-#define MC10 0x0400 /* Enable Mailbox 10 */
-#define MC11 0x0800 /* Enable Mailbox 11 */
-#define MC12 0x1000 /* Enable Mailbox 12 */
-#define MC13 0x2000 /* Enable Mailbox 13 */
-#define MC14 0x4000 /* Enable Mailbox 14 */
-#define MC15 0x8000 /* Enable Mailbox 15 */
-
-/* CAN_MC2 Masks */
-#define MC16 0x0001 /* Enable Mailbox 16 */
-#define MC17 0x0002 /* Enable Mailbox 17 */
-#define MC18 0x0004 /* Enable Mailbox 18 */
-#define MC19 0x0008 /* Enable Mailbox 19 */
-#define MC20 0x0010 /* Enable Mailbox 20 */
-#define MC21 0x0020 /* Enable Mailbox 21 */
-#define MC22 0x0040 /* Enable Mailbox 22 */
-#define MC23 0x0080 /* Enable Mailbox 23 */
-#define MC24 0x0100 /* Enable Mailbox 24 */
-#define MC25 0x0200 /* Enable Mailbox 25 */
-#define MC26 0x0400 /* Enable Mailbox 26 */
-#define MC27 0x0800 /* Enable Mailbox 27 */
-#define MC28 0x1000 /* Enable Mailbox 28 */
-#define MC29 0x2000 /* Enable Mailbox 29 */
-#define MC30 0x4000 /* Enable Mailbox 30 */
-#define MC31 0x8000 /* Enable Mailbox 31 */
-
-/* CAN_MD1 Masks */
-#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
-#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
-#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
-#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
-#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
-#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
-#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
-#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
-#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
-#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
-#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
-#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
-#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
-#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
-#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
-#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
-
-/* CAN_MD2 Masks */
-#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
-#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
-#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
-#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
-#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
-#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
-#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
-#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
-#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
-#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
-#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
-#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
-#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
-#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
-#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
-#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
-
-/* CAN_RMP1 Masks */
-#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
-#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
-#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
-#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
-#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
-#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
-#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
-#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
-#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
-#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
-#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
-#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
-#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
-#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
-#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
-#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
-
-/* CAN_RMP2 Masks */
-#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
-#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
-#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
-#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
-#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
-#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
-#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
-#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
-#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
-#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
-#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
-#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
-#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
-#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
-#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
-#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
-
-/* CAN_RML1 Masks */
-#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
-#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
-#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
-#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
-#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
-#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
-#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
-#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
-#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
-#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
-#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
-#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
-#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
-#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
-#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
-#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
-
-/* CAN_RML2 Masks */
-#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
-#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
-#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
-#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
-#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
-#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
-#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
-#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
-#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
-#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
-#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
-#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
-#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
-#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
-#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
-#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
-
-/* CAN_OPSS1 Masks */
-#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
-#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
-#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
-#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
-#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
-#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
-#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
-#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
-#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
-#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
-#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
-#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
-#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
-#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
-#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
-#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
-
-/* CAN_OPSS2 Masks */
-#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
-#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
-#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
-#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
-#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
-#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
-#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
-#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
-#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
-#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
-#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
-#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
-#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
-#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
-#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
-#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
-
-/* CAN_TRR1 Masks */
-#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
-#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
-#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
-#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
-#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
-#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
-#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
-#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
-#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
-#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
-#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
-#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
-#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
-#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
-#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
-#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
-
-/* CAN_TRR2 Masks */
-#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
-#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
-#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
-#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
-#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
-#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
-#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
-#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
-#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
-#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
-#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
-#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
-#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
-#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
-#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
-#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
-
-/* CAN_TRS1 Masks */
-#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
-#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
-#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
-#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
-#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
-#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
-#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
-#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
-#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
-#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
-#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
-#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
-#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
-#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
-#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
-#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
-
-/* CAN_TRS2 Masks */
-#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
-#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
-#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
-#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
-#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
-#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
-#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
-#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
-#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
-#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
-#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
-#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
-#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
-#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
-#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
-#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
-
-/* CAN_AA1 Masks */
-#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
-#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
-#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
-#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
-#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
-#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
-#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
-#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
-#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
-#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
-#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
-#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
-#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
-#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
-#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
-#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
-
-/* CAN_AA2 Masks */
-#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
-#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
-#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
-#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
-#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
-#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
-#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
-#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
-#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
-#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
-#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
-#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
-#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
-#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
-#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
-#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
-
-/* CAN_TA1 Masks */
-#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
-#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
-#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
-#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
-#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
-#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
-#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
-#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
-#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
-#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
-#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
-#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
-#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
-#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
-#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
-#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
-
-/* CAN_TA2 Masks */
-#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
-#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
-#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
-#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
-#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
-#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
-#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
-#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
-#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
-#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
-#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
-#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
-#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
-#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
-#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
-#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
-
-/* CAN_MBTD Masks */
-#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
-#define TDA 0x0040 /* Temporary Disable Acknowledge */
-#define TDR 0x0080 /* Temporary Disable Request */
-
-/* CAN_RFH1 Masks */
-#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
-#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
-#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
-#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
-#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
-#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
-#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
-#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
-#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
-#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
-#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
-#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
-#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
-#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
-#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
-#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
-
-/* CAN_RFH2 Masks */
-#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
-#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
-#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
-#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
-#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
-#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
-#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
-#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
-#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
-#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
-#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
-#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
-#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
-#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
-#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
-#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
-
-/* CAN_MBTIF1 Masks */
-#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
-#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
-#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
-#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
-#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
-#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
-#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
-#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
-#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
-#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
-#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
-#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
-#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
-#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
-#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
-#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBTIF2 Masks */
-#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
-#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
-#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
-#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
-#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
-#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
-#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
-#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
-#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
-#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
-#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
-#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
-#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
-#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
-#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
-#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBRIF1 Masks */
-#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
-#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
-#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
-#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
-#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
-#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
-#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
-#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
-#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
-#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
-#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
-#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
-#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
-#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
-#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
-#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBRIF2 Masks */
-#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
-#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
-#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
-#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
-#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
-#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
-#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
-#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
-#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
-#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
-#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
-#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
-#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
-#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
-#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
-#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBIM1 Masks */
-#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
-#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
-#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
-#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
-#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
-#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
-#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
-#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
-#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
-#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
-#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
-#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
-#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
-#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
-#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
-#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
-
-/* CAN_MBIM2 Masks */
-#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
-#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
-#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
-#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
-#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
-#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
-#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
-#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
-#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
-#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
-#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
-#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
-#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
-#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
-#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
-#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
-
-/* CAN_GIM Masks */
-#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
-#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
-#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
-#define BOIM 0x0008 /* Enable Bus Off Interrupt */
-#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
-#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
-#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
-#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
-#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
-#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
-#define ADIM 0x0400 /* Enable Access Denied Interrupt */
-
-/* CAN_GIS Masks */
-#define EWTIS 0x0001 /* TX Error Count IRQ Status */
-#define EWRIS 0x0002 /* RX Error Count IRQ Status */
-#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
-#define BOIS 0x0008 /* Bus Off IRQ Status */
-#define WUIS 0x0010 /* Wake-Up IRQ Status */
-#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
-#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
-#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
-#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
-#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
-#define ADIS 0x0400 /* Access Denied IRQ Status */
-
-/* CAN_GIF Masks */
-#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
-#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
-#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
-#define BOIF 0x0008 /* Bus Off IRQ Flag */
-#define WUIF 0x0010 /* Wake-Up IRQ Flag */
-#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
-#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
-#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
-#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
-#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
-#define ADIF 0x0400 /* Access Denied IRQ Flag */
-
-/* CAN_UCCNF Masks */
-#define UCCNF 0x000F /* Universal Counter Mode */
-#define UC_STAMP 0x0001 /* Timestamp Mode */
-#define UC_WDOG 0x0002 /* Watchdog Mode */
-#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
-#define UC_ERROR 0x0006 /* CAN Error Frame Count */
-#define UC_OVER 0x0007 /* CAN Overload Frame Count */
-#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
-#define UC_AA 0x0009 /* TX Abort Count */
-#define UC_TA 0x000A /* TX Successful Count */
-#define UC_REJECT 0x000B /* RX Message Rejected Count */
-#define UC_RML 0x000C /* RX Message Lost Count */
-#define UC_RX 0x000D /* Total Successful RX Messages Count */
-#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
-#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
-#define UCRC 0x0020 /* Universal Counter Reload/Clear */
-#define UCCT 0x0040 /* Universal Counter CAN Trigger */
-#define UCE 0x0080 /* Universal Counter Enable */
-
-/* CAN_ESR Masks */
-#define ACKE 0x0004 /* Acknowledge Error */
-#define SER 0x0008 /* Stuff Error */
-#define CRCE 0x0010 /* CRC Error */
-#define SA0 0x0020 /* Stuck At Dominant Error */
-#define BEF 0x0040 /* Bit Error Flag */
-#define FER 0x0080 /* Form Error Flag */
-
-/* CAN_EWR Masks */
-#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
-#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
-
#endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index f60c333fec667ea8c88f0023659e8d2ae9dcab8e..dbb6b1d83f6dc7a2d0dc1861f23d0856a1170bd0 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -498,6 +498,10 @@ static struct musb_hdrc_config musb_config = {
.num_eps = 8,
.dma_channels = 8,
.gpio_vrsel = GPIO_PH6,
+ /* Some custom boards need to be active low, just set it to "0"
+ * if it is the case.
+ */
+ .gpio_vrsel_active = 1,
};
static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 06919db00a7419df563e40a00ac65ca5220caa7c..6fcfb9187c357bcf1b69f5ae821fec5386f6dc6b 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -603,6 +603,10 @@ static struct musb_hdrc_config musb_config = {
.num_eps = 8,
.dma_channels = 8,
.gpio_vrsel = GPIO_PE7,
+ /* Some custom boards need to be active low, just set it to "0"
+ * if it is the case.
+ */
+ .gpio_vrsel_active = 1,
};
static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index ab04d137fd8bc585fb86c099709c938d6e26491e..0ed06c2366fe9ca744db5dd51393e4c573d733c3 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2104,677 +2104,6 @@
#define ECCCNT 0x3ff /* Transfer Count */
-/* Bit masks for CAN0_CONTROL */
-
-#define SRS 0x1 /* Software Reset */
-#define DNM 0x2 /* DeviceNet Mode */
-#define ABO 0x4 /* Auto Bus On */
-#define WBA 0x10 /* Wakeup On CAN Bus Activity */
-#define SMR 0x20 /* Sleep Mode Request */
-#define CSR 0x40 /* CAN Suspend Mode Request */
-#define CCR 0x80 /* CAN Configuration Mode Request */
-
-/* Bit masks for CAN0_STATUS */
-
-#define WT 0x1 /* CAN Transmit Warning Flag */
-#define WR 0x2 /* CAN Receive Warning Flag */
-#define EP 0x4 /* CAN Error Passive Mode */
-#define EBO 0x8 /* CAN Error Bus Off Mode */
-#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
-#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
-#define MBPTR 0x1f00 /* Mailbox Pointer */
-#define TRM 0x4000 /* Transmit Mode Status */
-#define REC 0x8000 /* Receive Mode Status */
-
-/* Bit masks for CAN0_DEBUG */
-
-#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
-#define DRI 0x2 /* Disable CANRX Input Pin */
-#define DTO 0x4 /* Disable CANTX Output Pin */
-#define DIL 0x8 /* Disable Internal Loop */
-#define MAA 0x10 /* Mode Auto-Acknowledge */
-#define MRB 0x20 /* Mode Read Back */
-#define CDE 0x8000 /* CAN Debug Mode Enable */
-
-/* Bit masks for CAN0_CLOCK */
-
-#define BRP 0x3ff /* CAN Bit Rate Prescaler */
-
-/* Bit masks for CAN0_TIMING */
-
-#define SJW 0x300 /* Synchronization Jump Width */
-#define SAM 0x80 /* Sampling */
-#define TSEG2 0x70 /* Time Segment 2 */
-#define TSEG1 0xf /* Time Segment 1 */
-
-/* Bit masks for CAN0_INTR */
-
-#define CANRX 0x80 /* Serial Input From Transceiver */
-#define CANTX 0x40 /* Serial Output To Transceiver */
-#define SMACK 0x8 /* Sleep Mode Acknowledge */
-#define GIRQ 0x4 /* Global Interrupt Request Status */
-#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
-#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
-
-/* Bit masks for CAN0_GIM */
-
-#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
-#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
-#define EPIM 0x4 /* Error Passive Interrupt Mask */
-#define BOIM 0x8 /* Bus Off Interrupt Mask */
-#define WUIM 0x10 /* Wakeup Interrupt Mask */
-#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
-#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
-#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
-#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
-#define ADIM 0x400 /* Access Denied Interrupt Mask */
-
-/* Bit masks for CAN0_GIS */
-
-#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
-#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
-#define EPIS 0x4 /* Error Passive Interrupt Status */
-#define BOIS 0x8 /* Bus Off Interrupt Status */
-#define WUIS 0x10 /* Wakeup Interrupt Status */
-#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
-#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
-#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
-#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
-#define ADIS 0x400 /* Access Denied Interrupt Status */
-
-/* Bit masks for CAN0_GIF */
-
-#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
-#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
-#define EPIF 0x4 /* Error Passive Interrupt Flag */
-#define BOIF 0x8 /* Bus Off Interrupt Flag */
-#define WUIF 0x10 /* Wakeup Interrupt Flag */
-#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
-#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
-#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
-#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
-#define ADIF 0x400 /* Access Denied Interrupt Flag */
-
-/* Bit masks for CAN0_MBTD */
-
-#define TDR 0x80 /* Temporary Disable Request */
-#define TDA 0x40 /* Temporary Disable Acknowledge */
-#define TDPTR 0x1f /* Temporary Disable Pointer */
-
-/* Bit masks for CAN0_UCCNF */
-
-#define UCCNF 0xf /* Universal Counter Configuration */
-#define UCRC 0x20 /* Universal Counter Reload/Clear */
-#define UCCT 0x40 /* Universal Counter CAN Trigger */
-#define UCE 0x80 /* Universal Counter Enable */
-
-/* Bit masks for CAN0_CEC */
-
-#define RXECNT 0xff /* Receive Error Counter */
-#define TXECNT 0xff00 /* Transmit Error Counter */
-
-/* Bit masks for CAN0_ESR */
-
-#define FER 0x80 /* Form Error */
-#define BEF 0x40 /* Bit Error Flag */
-#define SA0 0x20 /* Stuck At Dominant */
-#define CRCE 0x10 /* CRC Error */
-#define SER 0x8 /* Stuff Bit Error */
-#define ACKE 0x4 /* Acknowledge Error */
-
-/* Bit masks for CAN0_EWR */
-
-#define EWLTEC 0xff00 /* Transmit Error Warning Limit */
-#define EWLREC 0xff /* Receive Error Warning Limit */
-
-/* Bit masks for CAN0_AMxx_H */
-
-#define FDF 0x8000 /* Filter On Data Field */
-#define FMD 0x4000 /* Full Mask Data */
-#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
-#define BASEID 0x1ffc /* Base Identifier */
-#define EXTID_HI 0x3 /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_AMxx_L */
-
-#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
-#define DFM 0xffff /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_ID1 */
-
-#define AME 0x8000 /* Acceptance Mask Enable */
-#define RTR 0x4000 /* Remote Transmission Request */
-#define IDE 0x2000 /* Identifier Extension */
-#define BASEID 0x1ffc /* Base Identifier */
-#define EXTID_HI 0x3 /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_MBxx_ID0 */
-
-#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
-#define DFM 0xffff /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_TIMESTAMP */
-
-#define TSV 0xffff /* Time Stamp Value */
-
-/* Bit masks for CAN0_MBxx_LENGTH */
-
-#define DLC 0xf /* Data Length Code */
-
-/* Bit masks for CAN0_MBxx_DATA3 */
-
-#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */
-#define CAN_BYTE1 0xff /* Data Field Byte 1 */
-
-/* Bit masks for CAN0_MBxx_DATA2 */
-
-#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */
-#define CAN_BYTE3 0xff /* Data Field Byte 3 */
-
-/* Bit masks for CAN0_MBxx_DATA1 */
-
-#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */
-#define CAN_BYTE5 0xff /* Data Field Byte 5 */
-
-/* Bit masks for CAN0_MBxx_DATA0 */
-
-#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */
-#define CAN_BYTE7 0xff /* Data Field Byte 7 */
-
-/* Bit masks for CAN0_MC1 */
-
-#define MC0 0x1 /* Mailbox 0 Enable */
-#define MC1 0x2 /* Mailbox 1 Enable */
-#define MC2 0x4 /* Mailbox 2 Enable */
-#define MC3 0x8 /* Mailbox 3 Enable */
-#define MC4 0x10 /* Mailbox 4 Enable */
-#define MC5 0x20 /* Mailbox 5 Enable */
-#define MC6 0x40 /* Mailbox 6 Enable */
-#define MC7 0x80 /* Mailbox 7 Enable */
-#define MC8 0x100 /* Mailbox 8 Enable */
-#define MC9 0x200 /* Mailbox 9 Enable */
-#define MC10 0x400 /* Mailbox 10 Enable */
-#define MC11 0x800 /* Mailbox 11 Enable */
-#define MC12 0x1000 /* Mailbox 12 Enable */
-#define MC13 0x2000 /* Mailbox 13 Enable */
-#define MC14 0x4000 /* Mailbox 14 Enable */
-#define MC15 0x8000 /* Mailbox 15 Enable */
-
-/* Bit masks for CAN0_MC2 */
-
-#define MC16 0x1 /* Mailbox 16 Enable */
-#define MC17 0x2 /* Mailbox 17 Enable */
-#define MC18 0x4 /* Mailbox 18 Enable */
-#define MC19 0x8 /* Mailbox 19 Enable */
-#define MC20 0x10 /* Mailbox 20 Enable */
-#define MC21 0x20 /* Mailbox 21 Enable */
-#define MC22 0x40 /* Mailbox 22 Enable */
-#define MC23 0x80 /* Mailbox 23 Enable */
-#define MC24 0x100 /* Mailbox 24 Enable */
-#define MC25 0x200 /* Mailbox 25 Enable */
-#define MC26 0x400 /* Mailbox 26 Enable */
-#define MC27 0x800 /* Mailbox 27 Enable */
-#define MC28 0x1000 /* Mailbox 28 Enable */
-#define MC29 0x2000 /* Mailbox 29 Enable */
-#define MC30 0x4000 /* Mailbox 30 Enable */
-#define MC31 0x8000 /* Mailbox 31 Enable */
-
-/* Bit masks for CAN0_MD1 */
-
-#define MD0 0x1 /* Mailbox 0 Receive Enable */
-#define MD1 0x2 /* Mailbox 1 Receive Enable */
-#define MD2 0x4 /* Mailbox 2 Receive Enable */
-#define MD3 0x8 /* Mailbox 3 Receive Enable */
-#define MD4 0x10 /* Mailbox 4 Receive Enable */
-#define MD5 0x20 /* Mailbox 5 Receive Enable */
-#define MD6 0x40 /* Mailbox 6 Receive Enable */
-#define MD7 0x80 /* Mailbox 7 Receive Enable */
-#define MD8 0x100 /* Mailbox 8 Receive Enable */
-#define MD9 0x200 /* Mailbox 9 Receive Enable */
-#define MD10 0x400 /* Mailbox 10 Receive Enable */
-#define MD11 0x800 /* Mailbox 11 Receive Enable */
-#define MD12 0x1000 /* Mailbox 12 Receive Enable */
-#define MD13 0x2000 /* Mailbox 13 Receive Enable */
-#define MD14 0x4000 /* Mailbox 14 Receive Enable */
-#define MD15 0x8000 /* Mailbox 15 Receive Enable */
-
-/* Bit masks for CAN0_MD2 */
-
-#define MD16 0x1 /* Mailbox 16 Receive Enable */
-#define MD17 0x2 /* Mailbox 17 Receive Enable */
-#define MD18 0x4 /* Mailbox 18 Receive Enable */
-#define MD19 0x8 /* Mailbox 19 Receive Enable */
-#define MD20 0x10 /* Mailbox 20 Receive Enable */
-#define MD21 0x20 /* Mailbox 21 Receive Enable */
-#define MD22 0x40 /* Mailbox 22 Receive Enable */
-#define MD23 0x80 /* Mailbox 23 Receive Enable */
-#define MD24 0x100 /* Mailbox 24 Receive Enable */
-#define MD25 0x200 /* Mailbox 25 Receive Enable */
-#define MD26 0x400 /* Mailbox 26 Receive Enable */
-#define MD27 0x800 /* Mailbox 27 Receive Enable */
-#define MD28 0x1000 /* Mailbox 28 Receive Enable */
-#define MD29 0x2000 /* Mailbox 29 Receive Enable */
-#define MD30 0x4000 /* Mailbox 30 Receive Enable */
-#define MD31 0x8000 /* Mailbox 31 Receive Enable */
-
-/* Bit masks for CAN0_RMP1 */
-
-#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
-#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
-#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
-#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
-#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
-#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
-#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
-#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
-#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
-#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
-#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
-#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
-#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
-#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
-#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
-#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
-
-/* Bit masks for CAN0_RMP2 */
-
-#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
-#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
-#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
-#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
-#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
-#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
-#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
-#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
-#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
-#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
-#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
-#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
-#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
-#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
-#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
-#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
-
-/* Bit masks for CAN0_RML1 */
-
-#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
-#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
-#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
-#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
-#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
-#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
-#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
-#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
-#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
-#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
-#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
-#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
-#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
-#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
-#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
-#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
-
-/* Bit masks for CAN0_RML2 */
-
-#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
-#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
-#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
-#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
-#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
-#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
-#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
-#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
-#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
-#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
-#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
-#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
-#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
-#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
-#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
-#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
-
-/* Bit masks for CAN0_OPSS1 */
-
-#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
-
-/* Bit masks for CAN0_OPSS2 */
-
-#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
-#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
-
-/* Bit masks for CAN0_TRS1 */
-
-#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
-#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
-#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
-#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
-#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
-#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
-#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
-#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
-#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
-#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
-#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
-#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
-#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
-#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
-#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
-#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
-
-/* Bit masks for CAN0_TRS2 */
-
-#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
-#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
-#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
-#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
-#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
-#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
-#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
-#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
-#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
-#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
-#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
-#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
-#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
-#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
-#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
-#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
-
-/* Bit masks for CAN0_TRR1 */
-
-#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
-#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
-#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
-#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
-#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
-#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
-#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
-#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
-#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
-#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
-#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
-#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
-#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
-#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
-#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
-#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
-
-/* Bit masks for CAN0_TRR2 */
-
-#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
-#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
-#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
-#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
-#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
-#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
-#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
-#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
-#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
-#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
-#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
-#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
-#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
-#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
-#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
-#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
-
-/* Bit masks for CAN0_AA1 */
-
-#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
-#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
-#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
-#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
-#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
-#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
-#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
-#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
-#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
-#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
-#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
-#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
-#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
-#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
-#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
-#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
-
-/* Bit masks for CAN0_AA2 */
-
-#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
-#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
-#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
-#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
-#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
-#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
-#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
-#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
-#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
-#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
-#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
-#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
-#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
-#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
-#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
-#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
-
-/* Bit masks for CAN0_TA1 */
-
-#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
-#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
-#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
-#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
-#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
-#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
-#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
-#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
-#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
-#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
-#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
-#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
-#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
-#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
-#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
-#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
-
-/* Bit masks for CAN0_TA2 */
-
-#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
-#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
-#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
-#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
-#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
-#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
-#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
-#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
-#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
-#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
-#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
-#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
-#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
-#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
-#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
-#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
-
-/* Bit masks for CAN0_RFH1 */
-
-#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
-#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
-#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
-#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
-#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
-#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
-#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
-#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
-#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
-#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
-#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
-#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
-#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
-#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
-#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
-#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
-
-/* Bit masks for CAN0_RFH2 */
-
-#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
-#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
-#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
-#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
-#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
-#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
-#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
-#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
-#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
-#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
-#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
-#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
-#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
-#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
-#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
-#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
-
-/* Bit masks for CAN0_MBIM1 */
-
-#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
-#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
-#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
-#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
-#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
-#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
-#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
-#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
-#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
-#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
-#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
-#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
-#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
-#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
-#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
-#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
-
-/* Bit masks for CAN0_MBIM2 */
-
-#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
-#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
-#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
-#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
-#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
-#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
-#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
-#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
-#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
-#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
-#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
-#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
-#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
-#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
-#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
-#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
-
-/* Bit masks for CAN0_MBTIF1 */
-
-#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
-#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
-#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
-#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
-#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
-#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
-#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
-#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
-#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
-#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
-#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
-#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
-#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
-#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
-#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
-#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
-
-/* Bit masks for CAN0_MBTIF2 */
-
-#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
-#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
-#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
-#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
-#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
-#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
-#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
-#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
-#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
-#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
-#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
-#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
-#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
-#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
-#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
-#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
-
-/* Bit masks for CAN0_MBRIF1 */
-
-#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
-#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
-#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
-#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
-#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
-#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
-#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
-#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
-#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
-#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
-#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
-#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
-#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
-#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
-#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
-#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
-
-/* Bit masks for CAN0_MBRIF2 */
-
-#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
-#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
-#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
-#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
-#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
-#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
-#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
-#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
-#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
-#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
-#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
-#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
-#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
-#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
-#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
-#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
-
/* Bit masks for EPPIx_STATUS */
#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 5163e2c383c5201a2c59e5cab514660640d86bd6..bfcfa86db2b57ae5c13164d2ca78aefa12af0da6 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -44,6 +44,7 @@
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
+#include <linux/jiffies.h>
#include <linux/i2c-pca-platform.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -112,7 +113,7 @@ static struct resource bfin_i2c_pca_resources[] = {
struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
.gpio = -1,
.i2c_clock_speed = 330000,
- .timeout = 10000
+ .timeout = HZ,
};
/* PCA9564 I2C Bus driver */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 7ad8878bfa1815110a53220a1d96ab2c53df0476..1c8c4c7245c3868eb9cfcc62b783bac6a7c90755 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -92,26 +92,29 @@ static void __init search_IAR(void)
{
unsigned ivg, irq_pos = 0;
for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
- int irqn;
+ int irqN;
ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
- for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
- int iar_shift = (irqn & 7) * 4;
- if (ivg == (0xf &
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
- || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
- bfin_read32((unsigned long *)SIC_IAR0 +
- ((irqn % 32) >> 3) + ((irqn / 32) *
- ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
+ for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
+ int irqn;
+ u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
+#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
+ defined(CONFIG_BF538) || defined(CONFIG_BF539)
+ ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
#else
- bfin_read32((unsigned long *)SIC_IAR0 +
- (irqn >> 3)) >> iar_shift)) {
+ (irqN >> 3)
#endif
- ivg_table[irq_pos].irqno = IVG7 + irqn;
- ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
- ivg7_13[ivg].istop++;
- irq_pos++;
+ );
+
+ for (irqn = irqN; irqn < irqN + 4; ++irqn) {
+ int iar_shift = (irqn & 7) * 4;
+ if (ivg == (0xf & (iar >> iar_shift))) {
+ ivg_table[irq_pos].irqno = IVG7 + irqn;
+ ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
+ ivg7_13[ivg].istop++;
+ irq_pos++;
+ }
}
}
}
@@ -662,14 +665,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
#ifdef CONFIG_PM
int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
{
- unsigned gpio = irq_to_gpio(irq);
-
- if (state)
- gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
- else
- gpio_pm_wakeup_free(gpio);
-
- return 0;
+ return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state);
}
#endif
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index c1f1ccc846f067ade4556eb3c2e98db523a27a50..ea7f95f6bb4c92b4cd779a3c158bce85c9694361 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -20,35 +20,11 @@
#include <asm/dma.h>
#include <asm/dpmc.h>
-#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
-#define WAKEUP_TYPE PM_WAKE_HIGH
-#endif
-
-#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
-#define WAKEUP_TYPE PM_WAKE_LOW
-#endif
-
-#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
-#define WAKEUP_TYPE PM_WAKE_FALLING
-#endif
-
-#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
-#define WAKEUP_TYPE PM_WAKE_RISING
-#endif
-
-#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
-#define WAKEUP_TYPE PM_WAKE_BOTH_EDGES
-#endif
-
void bfin_pm_suspend_standby_enter(void)
{
unsigned long flags;
-#ifdef CONFIG_PM_WAKEUP_BY_GPIO
- gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
-#endif
-
local_irq_save_hw(flags);
bfin_pm_standby_setup();
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 7cecbaf0358ab03e0a42e5492475d7a241f31fd3..a17107a700d50cce38a1f581ba0e9b6c5a413c77 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -170,8 +170,8 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance)
kfree(msg);
break;
default:
- printk(KERN_CRIT "CPU%u: Unknown IPI message \
- 0x%lx\n", cpu, msg->type);
+ printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
+ cpu, msg->type);
kfree(msg);
break;
}
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 355b87aa6b9322da7c1e5074e0eb5170fe6d5de3..bb4e8fff4b556f14751e9502d407b6c3398679bf 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -15,23 +15,11 @@
#include "blackfin_sram.h"
/*
- * BAD_PAGE is the page that is used for page faults when linux
- * is out-of-memory. Older versions of linux just did a
- * do_exit(), but using this instead means there is less risk
- * for a process dying in kernel mode, possibly leaving a inode
- * unused etc..
- *
- * BAD_PAGETABLE is the accompanying page-table: it is initialized
- * to point to BAD_PAGE entries.
- *
- * ZERO_PAGE is a special page that is used for zero-initialized
- * data and COW.
+ * ZERO_PAGE is a special page that is used for zero-initialized data and COW.
+ * Let the bss do its zero-init magic so we don't have to do it ourselves.
*/
-static unsigned long empty_bad_page_table;
-
-static unsigned long empty_bad_page;
-
-static unsigned long empty_zero_page;
+char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
+EXPORT_SYMBOL(empty_zero_page);
#ifndef CONFIG_EXCEPTION_L1_SCRATCH
#if defined CONFIG_SYSCALL_TAB_L1
@@ -52,40 +40,26 @@ EXPORT_SYMBOL(cpu_pda);
void __init paging_init(void)
{
/*
- * make sure start_mem is page aligned, otherwise bootmem and
- * page_alloc get different views og the world
+ * make sure start_mem is page aligned, otherwise bootmem and
+ * page_alloc get different views of the world
*/
unsigned long end_mem = memory_end & PAGE_MASK;
- pr_debug("start_mem is %#lx virtual_end is %#lx\n", PAGE_ALIGN(memory_start), end_mem);
-
- /*
- * initialize the bad page table and bad page to point
- * to a couple of allocated pages
- */
- empty_bad_page_table = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
- empty_bad_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
- empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
- memset((void *)empty_zero_page, 0, PAGE_SIZE);
+ unsigned long zones_size[MAX_NR_ZONES] = {
+ [0] = 0,
+ [ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT,
+ [ZONE_NORMAL] = 0,
+#ifdef CONFIG_HIGHMEM
+ [ZONE_HIGHMEM] = 0,
+#endif
+ };
- /*
- * Set up SFC/DFC registers (user data space)
- */
+ /* Set up SFC/DFC registers (user data space) */
set_fs(KERNEL_DS);
- pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
+ pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
PAGE_ALIGN(memory_start), end_mem);
-
- {
- unsigned long zones_size[MAX_NR_ZONES] = { 0, };
-
- zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT;
- zones_size[ZONE_NORMAL] = 0;
-#ifdef CONFIG_HIGHMEM
- zones_size[ZONE_HIGHMEM] = 0;
-#endif
- free_area_init(zones_size);
- }
+ free_area_init(zones_size);
}
asmlinkage void __init init_pda(void)
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c
index 39b058564f62400db2b00af74127d13cd0d83fd4..7e2e674ed4440a6a0e333f0ddca5f29837394e13 100644
--- a/arch/blackfin/mm/isram-driver.c
+++ b/arch/blackfin/mm/isram-driver.c
@@ -43,13 +43,12 @@ static DEFINE_SPINLOCK(dtest_lock);
/* Takes a void pointer */
#define IADDR2DTEST(x) \
({ unsigned long __addr = (unsigned long)(x); \
- (__addr & 0x47F8) | /* address bits 14 & 10:3 */ \
- (__addr & 0x8000) << 23 | /* Bank A/B */ \
- (__addr & 0x0800) << 15 | /* address bit 11 */ \
- (__addr & 0x3000) << 4 | /* address bits 13:12 */ \
- (__addr & 0x8000) << 8 | /* address bit 15 */ \
- (0x1000000) | /* instruction access = 1 */ \
- (0x4); /* data array = 1 */ \
+ ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \
+ (1 << 24) | /* instruction access = 1 */ \
+ ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \
+ ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
+ (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \
+ (1 << 2); /* data array = 1 */ \
})
/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
@@ -196,7 +195,7 @@ EXPORT_SYMBOL(isram_memcpy);
#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
-#define TEST_LEN 0x100
+static int test_len = 0x20000;
static __init void hex_dump(unsigned char *buf, int len)
{
@@ -212,15 +211,15 @@ static __init int isram_read_test(char *sdram, void *l1inst)
pr_info("INFO: running isram_read tests\n");
/* setup some different data to play with */
- for (i = 0; i < TEST_LEN; ++i)
- sdram[i] = i;
- dma_memcpy(l1inst, sdram, TEST_LEN);
+ for (i = 0; i < test_len; ++i)
+ sdram[i] = i % 255;
+ dma_memcpy(l1inst, sdram, test_len);
/* make sure we can read the L1 inst */
- for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
+ for (i = 0; i < test_len; i += sizeof(uint64_t)) {
data1 = isram_read(l1inst + i);
memcpy(&data2, sdram + i, sizeof(data2));
- if (memcmp(&data1, &data2, sizeof(uint64_t))) {
+ if (data1 != data2) {
pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
l1inst + i, data1, data2);
++ret;
@@ -238,25 +237,25 @@ static __init int isram_write_test(char *sdram, void *l1inst)
pr_info("INFO: running isram_write tests\n");
/* setup some different data to play with */
- memset(sdram, 0, TEST_LEN * 2);
- dma_memcpy(l1inst, sdram, TEST_LEN);
- for (i = 0; i < TEST_LEN; ++i)
- sdram[i] = i;
+ memset(sdram, 0, test_len * 2);
+ dma_memcpy(l1inst, sdram, test_len);
+ for (i = 0; i < test_len; ++i)
+ sdram[i] = i % 255;
/* make sure we can write the L1 inst */
- for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
+ for (i = 0; i < test_len; i += sizeof(uint64_t)) {
memcpy(&data1, sdram + i, sizeof(data1));
isram_write(l1inst + i, data1);
data2 = isram_read(l1inst + i);
- if (memcmp(&data1, &data2, sizeof(uint64_t))) {
+ if (data1 != data2) {
pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
l1inst + i, data1, data2);
++ret;
}
}
- dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
- if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
+ dma_memcpy(sdram + test_len, l1inst, test_len);
+ if (memcmp(sdram, sdram + test_len, test_len)) {
pr_err("FAIL: isram_write() did not work properly\n");
++ret;
}
@@ -268,12 +267,12 @@ static __init int
_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
void *(*fmemcpy)(void *, const void *, size_t))
{
- memset(sdram, pattern, TEST_LEN);
- fmemcpy(l1inst, sdram, TEST_LEN);
- fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
- if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
+ memset(sdram, pattern, test_len);
+ fmemcpy(l1inst, sdram, test_len);
+ fmemcpy(sdram + test_len, l1inst, test_len);
+ if (memcmp(sdram, sdram + test_len, test_len)) {
pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
- smemcpy, l1inst, sdram, TEST_LEN, pattern);
+ smemcpy, l1inst, sdram, test_len, pattern);
return 1;
}
return 0;
@@ -292,12 +291,13 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
/* check read of small, unaligned, and hardware 64bit limits */
pr_info("INFO: running isram_memcpy (read) tests\n");
- for (i = 0; i < TEST_LEN; ++i)
- sdram[i] = i;
- dma_memcpy(l1inst, sdram, TEST_LEN);
+ /* setup some different data to play with */
+ for (i = 0; i < test_len; ++i)
+ sdram[i] = i % 255;
+ dma_memcpy(l1inst, sdram, test_len);
thisret = 0;
- for (i = 0; i < TEST_LEN - 32; ++i) {
+ for (i = 0; i < test_len - 32; ++i) {
unsigned char cmp[32];
for (j = 1; j <= 32; ++j) {
memset(cmp, 0, sizeof(cmp));
@@ -310,7 +310,7 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
pr_cont("\n");
if (++thisret > 20) {
pr_err("FAIL: skipping remaining series\n");
- i = TEST_LEN;
+ i = test_len;
break;
}
}
@@ -321,11 +321,11 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
/* check write of small, unaligned, and hardware 64bit limits */
pr_info("INFO: running isram_memcpy (write) tests\n");
- memset(sdram + TEST_LEN, 0, TEST_LEN);
- dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN);
+ memset(sdram + test_len, 0, test_len);
+ dma_memcpy(l1inst, sdram + test_len, test_len);
thisret = 0;
- for (i = 0; i < TEST_LEN - 32; ++i) {
+ for (i = 0; i < test_len - 32; ++i) {
unsigned char cmp[32];
for (j = 1; j <= 32; ++j) {
isram_memcpy(l1inst + i, sdram + i, j);
@@ -338,7 +338,7 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
pr_cont("\n");
if (++thisret > 20) {
pr_err("FAIL: skipping remaining series\n");
- i = TEST_LEN;
+ i = test_len;
break;
}
}
@@ -355,22 +355,30 @@ static __init int isram_test_init(void)
char *sdram;
void *l1inst;
- sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL);
- if (!sdram) {
- pr_warning("SKIP: could not allocate sdram\n");
- return 0;
+ /* Try to test as much of L1SRAM as possible */
+ while (test_len) {
+ test_len >>= 1;
+ l1inst = l1_inst_sram_alloc(test_len);
+ if (l1inst)
+ break;
}
-
- l1inst = l1_inst_sram_alloc(TEST_LEN);
if (!l1inst) {
- kfree(sdram);
pr_warning("SKIP: could not allocate L1 inst\n");
return 0;
}
+ pr_info("INFO: testing %#x bytes (%p - %p)\n",
+ test_len, l1inst, l1inst + test_len);
+
+ sdram = kmalloc(test_len * 2, GFP_KERNEL);
+ if (!sdram) {
+ sram_free(l1inst);
+ pr_warning("SKIP: could not allocate sdram\n");
+ return 0;
+ }
/* sanity check initial L1 inst state */
ret = 1;
- pr_info("INFO: running initial dma_memcpy checks\n");
+ pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
goto abort;
if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 49b2ff2c8b74bee191df47682bcbae227b5beac6..627e04b5ba9a8979be2149ecff27e52f6bb05458 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -256,7 +256,8 @@ static void *_sram_alloc(size_t size, struct sram_piece *pfree_head,
plast->next = pslot->next;
pavail = pslot;
} else {
- pavail = kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
+ /* use atomic so our L1 allocator can be used atomically */
+ pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC);
if (!pavail)
return NULL;