From babc5544c2933a5cbf9389679507dfa4911101ee Mon Sep 17 00:00:00 2001
From: Baruch Siach <baruch@tkos.co.il>
Date: Tue, 16 Oct 2018 13:50:53 +0300
Subject: [PATCH] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal
This reset signal controls the Marvell 1512 1G PHY.
Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index f03740d5ce624..f2e5b98f0c326 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -333,6 +333,10 @@ ge_phy: ethernet-phy@0 {
*/
marvell,reg-init = <3 16 0 0x1017>;
reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_copper_eth_phy_reset>;
+ reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
};
switch0: switch0@4 {
--
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