Kulkarni, Ganapatrao
authored
The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by:Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> [will: minor spelling and format fixes, dropped events list] Signed-off-by:
Will Deacon <will.deacon@arm.com>
Code owners
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| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| arm-ccn.txt | ||
| arm_dsu_pmu.txt | ||
| hisi-pmu.txt | ||
| qcom_l2_pmu.txt | ||
| qcom_l3_pmu.txt | ||
| thunderx2-pmu.txt | ||
| xgene-pmu.txt | ||