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Commit 343e64a6 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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clk: renesas: Add r8a77470 CPG Core Clock Definitions


Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
Manual.

Signed-off-by: default avatarBiju Das <biju.das@bp.renesas.com>
Reviewed-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
[geert: Use consecutive numbering]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent cdc749e2
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