cpus.yaml

# SPDX-License-Identifier: (GPL-2.0 OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V bindings for 'cpus' DT nodes

maintainers:
  - Paul Walmsley <paul.walmsley@sifive.com>
  - Palmer Dabbelt <palmer@sifive.com>

properties:
  compatible:
    items:
      - enum:
          - sifive,rocket0
          - sifive,e5
          - sifive,e51
          - sifive,u54-mc
          - sifive,u54
          - sifive,u5
      - const: riscv
    description:
      Identifies that the hart uses the RISC-V instruction set
      and identifies the type of the hart.

  mmu-type:
    allOf:
      - $ref: "/schemas/types.yaml#/definitions/string"
      - enum:
          - riscv,sv32
          - riscv,sv39
          - riscv,sv48
    description:
      Identifies the MMU address translation mode used on this
      hart.  These values originate from the RISC-V Privileged
      Specification document, available from
      https://riscv.org/specifications/

  riscv,isa:
    allOf:
      - $ref: "/schemas/types.yaml#/definitions/string"
      - enum:
          - rv64imac
          - rv64imafdc
    description:
      Identifies the specific RISC-V instruction set architecture
      supported by the hart.  These are documented in the RISC-V
      User-Level ISA document, available from
      https://riscv.org/specifications/

  timebase-frequency:
    type: integer
    minimum: 1
    description:
      Specifies the clock frequency of the system timer in Hz.
      This value is common to all harts on a single system image.

  interrupt-controller:
    type: object
    description: Describes the CPU's local interrupt controller

    properties:
      '#interrupt-cells':
        const: 1

      compatible:
        const: riscv,cpu-intc