Merge branch 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 RAS changes from Ingo Molnar: "The main changes in this cycle were: - Simplify the CMCI storm logic on Intel CPUs after yet another report about a race in the code (Borislav Petkov) - Enable the MCE threshold irq on AMD CPUs by default (Aravind Gopalakrishnan) - Add AMD-specific MCE-severity grading function. Further error recovery actions will be based on its output (Aravind Gopalakrishnan) - Documentation updates (Borislav Petkov) - ... assorted fixes and cleanups" * 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mce/severity: Fix warning about indented braces x86/mce: Define mce_severity function pointer x86/mce: Add an AMD severities-grading function x86/mce: Reindent __mcheck_cpu_apply_quirks() properly x86/mce: Use safe MSR accesses for AMD quirk x86/MCE/AMD: Enable thresholding interrupts by default if supported x86/MCE: Make mce_panic() fatal machine check msg in the same pattern x86/MCE/intel: Cleanup CMCI storm logic Documentation/acpi/einj: Correct and streamline text x86/MCE/AMD: Drop bogus const modifier from AMD's bank4_names()
Showing
- Documentation/acpi/apei/einj.txt 122 additions, 74 deletionsDocumentation/acpi/apei/einj.txt
- arch/x86/include/asm/mce.h 12 additions, 4 deletionsarch/x86/include/asm/mce.h
- arch/x86/kernel/cpu/mcheck/mce-internal.h 6 additions, 5 deletionsarch/x86/kernel/cpu/mcheck/mce-internal.h
- arch/x86/kernel/cpu/mcheck/mce-severity.c 65 additions, 1 deletionarch/x86/kernel/cpu/mcheck/mce-severity.c
- arch/x86/kernel/cpu/mcheck/mce.c 81 additions, 73 deletionsarch/x86/kernel/cpu/mcheck/mce.c
- arch/x86/kernel/cpu/mcheck/mce_amd.c 8 additions, 3 deletionsarch/x86/kernel/cpu/mcheck/mce_amd.c
- arch/x86/kernel/cpu/mcheck/mce_intel.c 42 additions, 21 deletionsarch/x86/kernel/cpu/mcheck/mce_intel.c
Loading
Please register or sign in to comment