clk: meson: add mpll pre-divider
mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble Signed-off-by:Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com>
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- drivers/clk/meson/axg.c 20 additions, 4 deletionsdrivers/clk/meson/axg.c
- drivers/clk/meson/axg.h 2 additions, 1 deletiondrivers/clk/meson/axg.h
- drivers/clk/meson/gxbb.c 20 additions, 3 deletionsdrivers/clk/meson/gxbb.c
- drivers/clk/meson/gxbb.h 2 additions, 1 deletiondrivers/clk/meson/gxbb.h
- drivers/clk/meson/meson8b.c 19 additions, 3 deletionsdrivers/clk/meson/meson8b.c
- drivers/clk/meson/meson8b.h 2 additions, 1 deletiondrivers/clk/meson/meson8b.h
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