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Unverified Commit 8ba3c521 authored by Olivier Moysan's avatar Olivier Moysan Committed by Mark Brown
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ASoC: stm32: i2s: fix IRQ clearing


Because of regmap cache, interrupts may not be cleared
as expected.
Declare IFCR register as write only and make writings
to IFCR register unconditional.

Signed-off-by: default avatarOlivier Moysan <olivier.moysan@st.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent ae3f563a
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