- Jun 07, 2019
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Keerthy authored
The patch adds k3 am654 compatible, specific properties and an example. Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- May 28, 2019
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Rob Herring authored
Convert the Arm PL061 GPIO controller binding to json-schema format. As I'm the author for all but the gpio-ranges line, make the schema dual GPL/BSD license. Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: linux-gpio@vger.kernel.org Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Apr 11, 2019
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Alexandre Belloni authored
The NXP PCA6416 is a variant of the PCA GPIO expander, with 16 GPIOs. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Mar 22, 2019
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Geert Uytterhoeven authored
The ON Semiconductor CAT9554 is a variant of the PCA953x GPIO expander, with 8 GPIOs and interrupt functionality. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com>
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- Feb 22, 2019
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Linus Walleij authored
This adds DT bindings for the IXP4xx GPIO controller. Cc: devicetree@vger.kernel.org Reviewed-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Feb 21, 2019
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Baolin Wang authored
Use SoC compatible string instead of wildcard string. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Baolin Wang <baolin.wang@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Feb 14, 2019
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Thomas Petazzoni authored
The NXP PCAL6416 is a variant of the PCA GPIO expander, with 16 GPIOs. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com>
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- Feb 13, 2019
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Thomas Petazzoni authored
This commit extends the flags that can be used in GPIO specifiers to indicate if a pull-up resistor or pull-down resistor should be enabled. While some pinctrl DT bindings already offer the capability of configuring pull-up/pull-down resistors at the pin level, a number of simple GPIO controllers don't have any pinmuxing capability, and therefore do not rely on the pinctrl DT bindings. Such simple GPIO controllers however sometimes allow to configure pull-up and pull-down resistors on a per-pin basis, and whether such resistors should be enabled or not is a highly board-specific HW characteristic. By using two additional bits of the GPIO flag specifier, we can easily allow the Device Tree to describe which GPIOs should have their pull-up or pull-down resistors enabled. Even though the two options are mutually exclusive, we still need two bits to encode at least three states: no pull-up/pull-down, pull-up, pull-down. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Feb 08, 2019
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Linus Walleij authored
This adds device tree bindings for the Gateworks PLD GPIO chip, a simple I2C GPIO controller. Cc: devicetree@vger.kernel.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Jan 16, 2019
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Otto Sabart authored
The cp110-system-controller0.txt file was renamed to cp110-system-controller.txt. Fixes: 4aa54969 ("dt-bindings: cp110: rename cp110 syscon file") Signed-off-by:
Otto Sabart <ottosabart@seberm.com> Signed-off-by:
Rob Herring <robh@kernel.org>
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- Dec 21, 2018
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Jan Kotas authored
This patch adds a DT binding documentation for Cadence GPIO controller. Signed-off-by:
Jan Kotas <jank@cadence.com> Reviewed-by:
Rob Herring <robh@kernel.org> [Removed interrupt-parent] Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Dec 20, 2018
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Andreas Klinger authored
Document properties reg and interrupts for OMAP GPIO controller bindings Also add unit address in node name of the example Signed-off-by:
Andreas Klinger <ak@it-klinger.de> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Rob Herring <robh@kernel.org>
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- Dec 17, 2018
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Fabrizio Castro authored
Document Renesas' RZ/G2E (R8A774C0) GPIO blocks compatibility within the relevant dt-bindings. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Dec 07, 2018
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Vladimir Zapolskiy authored
From LPC18xx and LPC43xx User Manuals the GPIO controller consists of the following weakly connected blocks: * GPIO pin interrupt block at 0x40087000, * GPIO GROUP0 interrupt block at 0x40088000, * GPIO GROUP1 interrupt block at 0x40089000, * GPIO port block at 0x400F4000. While all 4 sub-controller blocks have their own I/O addresses, moreover all 3 interrupt blocks are APB0 peripherals and high-speed GPIO block is an AHB slave, according to the hardware manual interrupt controllers and GPIO controller block are seen as a single device, all 4 sub-controllers have the shared reset signal RGU #28 and the same shared clock to access registers CLK_Mx_GPIO on CCU1. The change adds descriptions of the currently missing interrupt controller blocks found on GPIO controller, new added properties are 'reg-names', 'resets', 'interrupt-controller' and '#interrupt-cells', also the example is updated to reflect the changes in device tree binding description. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Nov 26, 2018
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Phil Edworthy authored
The sub-nodes should not be called gpio-controller, but simply gpio. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Nov 05, 2018
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A.s. Dong authored
On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe disabled by default. Users have to make sure it's enabled before being able to access controller registers, otherwise an external abort error may occur. Let's add the optional clocks property to handle this case. For ULP GPIO clock, it includes two separate clocks: one is for GPIO controller Input/Output function clock while another is GPIO port control clock for interrupt function. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stefan Agner <stefan@agner.ch> Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Oct 10, 2018
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Eugeniy Paltsev authored
This patch adds documentation of device tree bindings for the Synopsys GPIO via CREG driver. Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Sep 25, 2018
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Biju Das authored
Renesas RZ/G1N (R8A7744) SoC GPIO blocks are identical to the R-Car Gen2 family. Add support for its GPIO controllers. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Sep 20, 2018
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Linus Walleij authored
We remove the references to anything but two-cell GPIO specifiers and just mention that controllers need to specify their bindings and that we strongly recommend two-cell bindings. Cc: devicetree@vger.kernel.org Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
In 2011 the commit bf859f84 ("gpio/dt: Refine GPIO device tree binding") introduced an experimental BNF notation for defining a regular grammar for the GPIO phandles used by different devices. This was an interesting approach, and shows that we have long nutured the idea to formally verify device tree files using regular grammar. Most if not all other bindings use natural language to define the bindings, and the recent thinking for verifying device tree files is to use JSON schemas in separate definitions. Cut the BNF business and replace it with natural language so that it becomes more human-readable for now. Cc: devicetree@vger.kernel.org Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Kumar Gala <galak@kernel.crashing.org> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Sep 11, 2018
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Wolfram Sang authored
The ';' was missing. And cosmetic: there was a space too much. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Aug 29, 2018
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Fabrizio Castro authored
Document Renesas' RZ/G2M (R8A774A1) GPIO blocks compatibility within the relevant dt-bindings. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Paul Cercueil authored
The pinctrl-ingenic driver now supports the JZ4725B SoC. Furthermore, the gpio-ingenic driver was dropped and the pinctrl-ingenic driver is now responsible for providing the GPIO functionality. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Biju Das authored
Update the DT bindings documentation with the optional gpio-reserved-ranges properties. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Aug 06, 2018
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Levin Du authored
In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute control, can also be used for general purpose. It is manipulated by the GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can also be set in the same way. Currently this GRF GPIO controller only supports the mute pin. If needed in the future, the HDMI pins support can also be added. Signed-off-by:
Levin Du <djw@t-chip.com.cn> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Jul 25, 2018
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Rob Herring authored
'interrupt-parent' is often documented as part of define bindings, but it is really outside the scope of a device binding. It's never required in a given node as it is often inherited from a parent node. Or it can be implicit if a parent node is an 'interrupt-controller' node. So remove it from all the binding files. Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by:
Rob Herring <robh@kernel.org>
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- Jul 10, 2018
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Geert Uytterhoeven authored
The device can optionally supply an interrupt, hence document that. Add required GPIO properties to the example (extracted from a patch by Wolfram Sang). Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Rob Herring <robh@kernel.org>
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- Jul 09, 2018
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Anson Huang authored
Some i.MX SoCs have GPIO clock gate in CCM, accessing GPIO registers needs to enable GPIO clock gate first, i.MX GPIO driver will enable clock gate if there is clock property in GPIO node of dtb, add optional property to i.MX GPIO binding doc. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Sergio Paracuellos authored
Add a devicetree binding documentation for the mt7621 gpio. Signed-off-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by:
NeilBrown <neil@brown.name> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Jul 02, 2018
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Mikko Perttunen authored
The Tegra194 GPIO controller is similar to the one in Tegra186. Add relevant information to the device tree binding documentation. Signed-off-by:
Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by:
Rob Herring <robh@kernel.org> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Jun 26, 2018
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Jonathan Neuschäfer authored
Multiple binding documents have various forms of unbalanced quotation marks. Fix them. Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by:
Krzysztof Kozlowski <krzk@kernel.org> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
Rob Herring <robh@kernel.org>
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- Jun 18, 2018
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Sergei Shtylyov authored
Renesas R-Car V3H (R8A77980) SoC also has the R-Car gen3 compatible GPIO controllers, so document the SoC specific bindings. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- May 23, 2018
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Yoshihiro Shimoda authored
Add compatible string for R-Car E3 (r8a77990) in gpio-rcar. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- May 16, 2018
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H. Nikolaus Schaller authored
It is not completely obvious that these are required and how to use them. So we provide a tested example. Signed-off-by:
H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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H. Nikolaus Schaller authored
Hardware can have a switchable Vcc supply, so let's add it to the bindings (the current Linux driver code already supports it). Signed-off-by:
H. Nikolaus Schaller <hns@goldelico.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Phil Edworthy authored
The DesignWare GPIO IP can be configured for either 1 interrupt or 1 per GPIO in port A, but the driver currently only supports 1 interrupt. See the DesignWare DW_apb_gpio Databook description of the 'GPIO_INTR_IO' parameter. This change allows the driver to work with up to 32 interrupts, it will get as many interrupts as specified in the DT 'interrupts' property. It doesn't do anything clever with the different interrupts, it just calls the same handler used for single interrupt hardware. ACPI companion code provided by Hoan Tran <hotran@apm.com>. This was tested on X-Gene by Hoan. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by:
Rob Herring <robh@kernel.org> Acked-by:
Lee Jones <lee.jones@linaro.org> Acked-by:
Hoan Tran <hotran@apm.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jacopo Mondi authored
Add compatible string for R-Car M3-N (r8a77965) in gpio-rcar. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Biju Das authored
Renesas RZ/G1C (R8A77470) SoC GPIO blocks are identical to the R-Car Gen2 family. Add support for its GPIO controllers. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Chris Paterson <chris.paterson2@renesas.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- Mar 27, 2018
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Baolin Wang authored
This patch adds the device tree bindings for the Spreadtrum EIC controller. The EIC can be seen as a special type of GPIO, which can only be used as input mode. Signed-off-by:
Baolin Wang <baolin.wang@linaro.org> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Stephen Boyd authored
Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Introduce a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Cc: Grant Likely <grant.likely@secretlab.ca> Cc: <devicetree@vger.kernel.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Rob Herring <robh@kernel.org> Tested-by:
Timur Tabi <timur@codeaurora.org> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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