- Jul 15, 2019
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Mauro Carvalho Chehab authored
All those new files I added are under GPL v2.0 license. Add the corresponding SPDX headers to them. Signed-off-by:
Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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Mauro Carvalho Chehab authored
Now that several arch documents were converted to ReST, add their indexes to Documentation/index.rst and remove the :orphan: from them. Signed-off-by:
Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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Mauro Carvalho Chehab authored
Converts ARM the text files to ReST, preparing them to be an architecture book. The conversion is actually: - add blank lines and identation in order to identify paragraphs; - fix tables markups; - add some lists markups; - mark literal blocks; - adjust title markups. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by:
Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Reviewed-by Corentin Labbe <clabbe.montjoie@gmail.com> # For sun4i-ss
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- Jun 08, 2019
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Mauro Carvalho Chehab authored
Sphinx doesn't like orphan documents: Documentation/accelerators/ocxl.rst: WARNING: document isn't included in any toctree Documentation/arm/stm32/overview.rst: WARNING: document isn't included in any toctree Documentation/arm/stm32/stm32f429-overview.rst: WARNING: document isn't included in any toctree Documentation/arm/stm32/stm32f746-overview.rst: WARNING: document isn't included in any toctree Documentation/arm/stm32/stm32f769-overview.rst: WARNING: document isn't included in any toctree Documentation/arm/stm32/stm32h743-overview.rst: WARNING: document isn't included in any toctree Documentation/arm/stm32/stm32mp157-overview.rst: WARNING: document isn't included in any toctree Documentation/gpu/msm-crash-dump.rst: WARNING: document isn't included in any toctree Documentation/interconnect/interconnect.rst: WARNING: document isn't included in any toctree Documentation/laptops/lg-laptop.rst: WARNING: document isn't included in any toctree Documentation/powerpc/isa-versions.rst: WARNING: document isn't included in any toctree Documentation/virtual/kvm/amd-memory-encryption.rst: WARNING: document isn't included in any toctree Documentation/virtual/kvm/vcpu-requests.rst: WARNING: document isn't included in any toctree So, while they aren't on any toctree, add :orphan: to them, in order to silent this warning. Signed-off-by:
Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Acked-by:
Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Jun 07, 2019
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George G. Davis authored
Fix a couple of s/poped/popped/ typos. Signed-off-by:
George G. Davis <george_davis@mentor.com> Acked-by:
Steven Rostedt (VMware) <rostedt@goodmis.org> Acked-by:
Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Feb 12, 2019
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Nathan Chancellor authored
While building arm32 allyesconfig, I ran into the following errors: arch/arm/lib/xor-neon.c:17:2: error: You should compile this file with '-mfloat-abi=softfp -mfpu=neon' In file included from lib/raid6/neon1.c:27: /home/nathan/cbl/prebuilt/lib/clang/8.0.0/include/arm_neon.h:28:2: error: "NEON support not enabled" Building V=1 showed NEON_FLAGS getting passed along to Clang but __ARM_NEON__ was not getting defined. Ultimately, it boils down to Clang only defining __ARM_NEON__ when targeting armv7, rather than armv6k, which is the '-march' value for allyesconfig. >From lib/Basic/Targets/ARM.cpp in the Clang source: // This only gets set when Neon instructions are actually available, unlike // the VFP define, hence the soft float and arch check. This is subtly // different from gcc, we follow the intent which was that it should be set // when Neon instructions are actually available. if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { Builder.defineMacro("__ARM_NEON", "1"); Builder.defineMacro("__ARM_NEON__"); // current AArch32 NEON implementations do not support double-precision // floating-point even when it is present in VFP. Builder.defineMacro("__ARM_NEON_FP", "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP)); } Ard Biesheuvel recommended explicitly adding '-march=armv7-a' at the beginning of the NEON_FLAGS definitions so that __ARM_NEON__ always gets definined by Clang. This doesn't functionally change anything because that code will only run where NEON is supported, which is implicitly armv7. Link: https://github.com/ClangBuiltLinux/linux/issues/287 Suggested-by:
Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Acked-by:
Nicolas Pitre <nico@linaro.org> Reviewed-by:
Nick Desaulniers <ndesaulniers@google.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk>
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- Nov 20, 2018
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Will Deacon authored
Whilst making an unrelated change to some Documentation, Linus sayeth: | Afaik, even in Britain, "whilst" is unusual and considered more | formal, and "while" is the common word. | | [...] | | Can we just admit that we work with computers, and we don't need to | use þe eald Englisc spelling of words that most of the world never | uses? dictionary.com refers to the word as "Chiefly British", which is probably an undesirable attribute for technical documentation. Replace all occurrences under Documentation/ with "while". Cc: David Howells <dhowells@redhat.com> Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michael Halcrow <mhalcrow@google.com> Cc: Jonathan Corbet <corbet@lwn.net> Reported-by:
Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Sep 09, 2018
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Henrik Austad authored
This is a respin with a wider audience (all that get_maintainer returned) and I know this spams a *lot* of people. Not sure what would be the correct way, so my apologies for ruining your inbox. The 00-INDEX files are supposed to give a summary of all files present in a directory, but these files are horribly out of date and their usefulness is brought into question. Often a simple "ls" would reveal the same information as the filenames are generally quite descriptive as a short introduction to what the file covers (it should not surprise anyone what Documentation/sched/sched-design-CFS.txt covers) A few years back it was mentioned that these files were no longer really needed, and they have since then grown further out of date, so perhaps it is time to just throw them out. A short status yields the following _outdated_ 00-INDEX files, first counter is files listed in 00-INDEX but missing in the directory, last is files present but not listed in 00-INDEX. List of outdated 00-INDEX: Documentation: (4/10) Documentation/sysctl: (0/1) Documentation/timers: (1/0) Documentation/blockdev: (3/1) Documentation/w1/slaves: (0/1) Documentation/locking: (0/1) Documentation/devicetree: (0/5) Documentation/power: (1/1) Documentation/powerpc: (0/5) Documentation/arm: (1/0) Documentation/x86: (0/9) Documentation/x86/x86_64: (1/1) Documentation/scsi: (4/4) Documentation/filesystems: (2/9) Documentation/filesystems/nfs: (0/2) Documentation/cgroup-v1: (0/2) Documentation/kbuild: (0/4) Documentation/spi: (1/0) Documentation/virtual/kvm: (1/0) Documentation/scheduler: (0/2) Documentation/fb: (0/1) Documentation/block: (0/1) Documentation/networking: (6/37) Documentation/vm: (1/3) Then there are 364 subdirectories in Documentation/ with several files that are missing 00-INDEX alltogether (and another 120 with a single file and no 00-INDEX). I don't really have an opinion to whether or not we /should/ have 00-INDEX, but the above 00-INDEX should either be removed or be kept up to date. If we should keep the files, I can try to keep them updated, but I rather not if we just want to delete them anyway. As a starting point, remove all index-files and references to 00-INDEX and see where the discussion is going. Signed-off-by:
Henrik Austad <henrik@austad.us> Acked-by:
"Paul E. McKenney" <paulmck@linux.vnet.ibm.com> Just-do-it-by:
Steven Rostedt <rostedt@goodmis.org> Reviewed-by:
Jens Axboe <axboe@kernel.dk> Acked-by:
Paul Moore <paul@paul-moore.com> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by:
Mark Brown <broonie@kernel.org> Acked-by:
Mike Rapoport <rppt@linux.vnet.ibm.com> Cc: [Almost everybody else] Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Aug 30, 2018
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Krzysztof Kozlowski authored
Suspend to RAM on Odroid XU3/XU4/HC1 family (Exynos5422) causes imprecise abort: PM: Syncing filesystems ... done. Freezing user space processes ... (elapsed 0.003 seconds) done. OOM killer disabled. Freezing remaining freezable tasks ... (elapsed 0.003 seconds) done. wake enabled for irq 139 Disabling non-boot CPUs ... IRQ51 no longer affine to CPU1 IRQ52 no longer affine to CPU2 IRQ53 no longer affine to CPU3 IRQ54 no longer affine to CPU4 IRQ55 no longer affine to CPU5 IRQ56 no longer affine to CPU6 cpu cpu4: Dropping the link to regulator.40 IRQ57 no longer affine to CPU7 Unhandled fault: external abort on non-linefetch (0x1008) at 0xf081a028 Internal error: : 1008 [#1] PREEMPT SMP ARM with last call trace in exynos_suspend_enter(). The abort is caused by writing to register in secure part of sysram. Boards booted under secure firmware (e.g. Hardkernel Odroid boards) should access non-secure sysram. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org>
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- May 16, 2018
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Thomas Hebb authored
Remove dead links, make spacing consistent, and note that the family was acquired by Synaptics in 2017. Signed-off-by:
Thomas Hebb <tommyhebb@gmail.com> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- May 03, 2018
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Kishon Vijay Abraham I authored
From 4.18 kernel, all the MMC controller instances in DRA7 are programmed using sdhci based driver (sdhci-omap.c). Document this new requirement here. Both omap2plus_defconfig and multi_v7_defconfig has CONFIG_MMC_SDHCI_OMAP enabled. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Mar 06, 2018
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Robin Murphy authored
The arm-ccn driver is purely a perf driver for the CCN PMU, not a bus driver in the sense of the other residents of drivers/bus/, so let's move it to the appropriate place for SoC PMU drivers. Not to mention moving the documentation accordingly as well. Acked-by:
Pawel Moll <pawel.moll@arm.com> Acked-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Robin Murphy <robin.murphy@arm.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Mar 05, 2018
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Ludovic Barre authored
This patch adds initial support of STM32MP157 microprocessor (MPU) based on Arm Cortex-A7. New Cortex-A infrastructure (gic, timer,...) are selected if ARCH_MULTI_V7 is defined. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com>
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Ludovic Barre authored
This patch prepares the STM32 machine for the integration of Cortex-A based microprocessor (MPU), on top of the existing Cortex-M microcontroller family (MCU). Since both MCUs and MPUs are sharing common hardware blocks we can keep using ARCH_STM32 flag for most of them. If a hardware block is specific to one family we can use either ARM_SINGLE_ARMV7M or ARCH_MULTI_V7 flag. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com>
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Ludovic Barre authored
This patch rewrites stm32 documentation to rst (ReStructuredText) format. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com>
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Alexandre Torgue authored
Add new st,stm32f769 compatible machine name for STM32F769 MCU and update documentation. Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com>
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- Feb 28, 2018
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Nicolas Ferre authored
We move the former Atmel wording to the the new Microchip name for this SoC family. With the name of the directory we also change the content in relation with the update of the MAINTAINERS file. The Datasheet links now point to real documents instead of 404s. Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com>
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- Feb 16, 2018
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Boris Brezillon authored
As part of the process of sharing more code between different NAND based devices, we need to move all raw NAND related code to the raw/ subdirectory. Signed-off-by:
Boris Brezillon <boris.brezillon@bootlin.com>
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- Sep 22, 2017
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Icenowy Zheng authored
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Icenowy Zheng authored
The Allwinner V3s SoC is not quad-core, but single-core. Fix this in the README file. Fixes: b074fede ("arm: sunxi: add support for V3s SoC") Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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- Jul 17, 2017
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Geert Uytterhoeven authored
All low-level PM/SMP code using virt_to_phys() should actually use __pa_symbol() against kernel symbols. Update the documentation to move away from virt_to_phys(). Cfr. commit 6996cbb2372189f7 ("ARM: 8641/1: treewide: Replace uses of virt_to_phys with __pa_symbol") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Jun 02, 2017
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Alexandre Belloni authored
The Atmel sams70, samv70 and samv71 are Cortex-M7 based MCUs that can run Linux (without MMU). Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com>
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- Apr 20, 2017
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Perr Zhang authored
the path in the example cmd is out of date, and the path for now is also mentioned in the same file Signed-off-by:
Perr Zhang <strongbox8@zoho.com> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Mar 24, 2017
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Alexandre TORGUE authored
The STM32H743 is a Cortex-M7 MCU running at 400MHz and containing 1MBytes internal RAM. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com>
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- Jan 20, 2017
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Icenowy Zheng authored
Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB integrated DRAM, and several peripherals. Signed-off-by:
Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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- Jan 02, 2017
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Icenowy Zheng authored
Allwinner H2+ is a quad-core Cortex-A7 SoC. It is very like H3, that they share the same SoC ID (0x1680), and H3 memory maps as well as drivers works well on the SoC. Signed-off-by:
Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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- Nov 15, 2016
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Alexandre TORGUE authored
Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com>
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- Oct 24, 2016
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Mauro Carvalho Chehab authored
The previous patch renamed several files that are cross-referenced along the Kernel documentation. Adjust the links to point to the right places. Signed-off-by:
Mauro Carvalho Chehab <mchehab@s-opensource.com>
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- Oct 10, 2016
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Shuah Khan authored
Update 00-INDEX files with the current file list to reflect the runnable code move. Acked-by:
Michal Marek <mmarek@suse.com> Acked-by:
Jonathan Corbet <corbet@lwn.net> Reviewed-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Shuah Khan <shuahkh@osg.samsung.com>
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- Sep 08, 2016
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Maxime Ripard authored
The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family. It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S), but some controllers missing too (Ethernet, less I2C, less UARTs). Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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- Aug 18, 2016
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Icenowy Zheng authored
Now, the A83T and A64 SoC user manuals are available. Update the documentation to add the links. An updated version of A83T datasheet is also included now. Signed-off-by:
Icenowy Zheng <icenowy@aosc.xyz> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Aug 17, 2016
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Pawel Moll authored
XP can provide events from two sources: watchpoints, observing traffic on device ports and PMU looking at internal buses. Unfortunately the sysfs definition of the PMU events was requiring port number (instead of bus number) and direction (the buses are unidirectional), as these fields were shared with the watchpoint event. Although it does not introduce a major problem (port can be used as bus alias and direction is simply ignored for XP PMU events), it's better to fix it now, before external tools start depending on this behaviour. Signed-off-by:
Pawel Moll <pawel.moll@arm.com>
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- Jun 21, 2016
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Nicolas Ferre authored
Update the Atmel SoC entry for SAMA5D2 with all the product variants. Add the datasheet web link, now that it's available, for instant access to full product documentation. Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com>
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- Apr 28, 2016
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Kees Cook authored
This fixes several spelling mistakes in the Documentation/ tree, which are caught by checkpatch.pl's spell checking. Signed-off-by:
Kees Cook <keescook@chromium.org> Reviewed-by:
Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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- Feb 19, 2016
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Thomas Petazzoni authored
As we are adding support for the Armada 7K and 8K families, this commit adds them to the Marvell documentation listing all supported SoCs, together with references to their Product Brief, Homepage and Device Tree files. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
The Armada 38x Functional Spec is now available (after registration unfortunately), so add a link to it. While at it, fix a typo in the reference to the Armada 38x product page. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
In preparation to the introduction of other SoCs in the ARMv8 Armada EBU family, this commit tweaks the existing description of Armada 37xx by making the core, homepage and other informations be visible "under" the Armada 37xx item. Indeed, the new SoCs will not share the same core or homepage. In addition, a link to the Product Brief is added. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Arnd Bergmann authored
I'm still getting confused regarding which core specifically is used in which SoC, so I've added some more detail to the Marvell README file. I got most of this from random sources on the internet, so it's possible that some of the information is wrong, but most of it should be pretty obvious. There are a few remaining points I could not find out: * The CPU core in Orion 88F6183 * The difference (if any) between PJ4B-MP and PJ4C * The naming of Feroceon/Jolteon/Flareon/Sheeva/Mohawk/PJ1/PJ4 is still confusing, as they tend to overlap. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> [Thomas: - move Armada SP out from the EBU family into its own "Storage" family. This chip is indeed not part of the EBU family. - fixed the URL for the Armada SP information, since the link of the original patch no longer existed - explicitly indicate that there is no support in upstream for the Armada SP - indent the "Core: " description for the Armada XP to be clearly under the Armada XP category, so that it is clear it applies to Armada XP only, and not other cores of the EBU family.] Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Feb 17, 2016
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Masanari Iida authored
This patch fix a spelling typo found in clksrc-change-registers.awk. Signed-off-by:
Masanari Iida <standby24x7@gmail.com> Signed-off-by:
Jonathan Corbet <corbet@lwn.net>
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Gregory CLEMENT authored
Now that we support Armada 37xx, let's add this family of SoC to the Marvell documentation, and a reference to a link with more details about those processors. As for Armda 39x, no datasheet is publicly available at this time. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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