- Jun 07, 2019
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Manivannan Sadhasivam authored
Add drive strength support for Bitmain BM1880 SoC. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Manivannan Sadhasivam authored
Document drive strength settings for Bitmain BM1880 SoC. Signed-off-by:
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Young Xiao authored
platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. Signed-off-by:
Young Xiao <92siuyang@gmail.com> Reviewed-by:
Ray Jui <ray.jui@broadcom.com> Signed-off-by:
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Anson Huang authored
The i.MX8MM pinfunc head file is located in DT folder, correct it. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
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Linus Walleij authored
Some files were missing the appropriate SPDX tags so fixed it up. Signed-off-by:
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- Jun 01, 2019
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YueHaibing authored
drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function bcm2835_pctl_dt_node_to_map: drivers/pinctrl/bcm/pinctrl-bcm2835.c:720:8: error: implicit declaration of function pinconf_generic_dt_node_to_map_all; drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function bcm2835_pinctrl_probe: drivers/pinctrl/bcm/pinctrl-bcm2835.c:1022:15: error: struct gpio_chip has no member named of_node pc->gpio_chip.of_node = np; Reported-by:
Hulk Robot <hulkci@huawei.com> Fixes: 0de70495 ("pinctrl: bcm2835: Add support for generic pinctrl binding") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Linus Walleij authored
Using STM32 as guinea pig after Alex's initial positive test to see if this is something we should encourage in general and make default behaviour. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: -
Nicolas Boichat authored
Setting this up will configure wake from suspend properly, and wake only for the interrupts that are setup in wake_mask, not all interrupts. Signed-off-by:
Nicolas Boichat <drinkcat@chromium.org> Acked-by:
Sean Wang <sean.wang@kernel.org> Signed-off-by:
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Nicolas Boichat authored
pinctrl variants that include pinctrl-paris.h (and not pinctrl-mtk-common.h) also need to use pm_ops to setup wake mask properly, so copy over the pm_ops from common to paris variant. It is not easy to merge the 2 copies (or move mtk_eint_suspend/resume to mtk-eint.c), as we need to dereference pctrl->eint, and struct mtk_pinctrl *pctl has a different structure definition for v1 and v2 (which is what paris variant uses). Signed-off-by:
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Neil Armstrong authored
Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Neil Armstrong authored
Signed-off-by:
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Neil Armstrong authored
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Neil Armstrong authored
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Neil Armstrong authored
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Krishna Yarlagadda authored
Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled dynamically at runtime. This driver supports change pinmux for these pins. Pinmux for rest of the pins is set statically by bootloader and will not be changed by this driver Signed-off-by:
Krishna Yarlagadda <kyarlagadda@nvidia.com> Signed-off-by:
Suresh Mangipudi <smangipudi@nvidia.com> Tested-by:
Vidya Sagar <vidyas@nvidia.com> Signed-off-by:
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Krishna Yarlagadda authored
Tegra194 chip has 32 bit pinctrl registers. Existing register defines in header are only 16 bit. Modified common pinctrl-tegra driver to support 32 bit registers of Tegra 194 and later chips. Signed-off-by:
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Krishna Yarlagadda authored
Add binding doc for Tegra 194 pinctrl driver. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- May 27, 2019
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Colin Ian King authored
The spelling of configured is incorrect in the documentation. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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- May 24, 2019
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Manivannan Sadhasivam authored
Add pinconf support for Bitmain BM1880 SoC. Pinconf support includes pin bias, slew rate and schmitt trigger. Drive strength support will be added later. Signed-off-by:
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Manivannan Sadhasivam authored
Document pinconf bindings for Bitmain BM1880 SoC. Signed-off-by:
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Manivannan Sadhasivam authored
Rework the BM1880 SoC pinmux handling by removing the BM1880_PINMUX_FUNCTION_MUX define and merging it with the BM1880_PINMUX_FUNCTION definition. Since the PWM muxing is handled by generic pin controller in the SoC itself, there is no need to have a dedicated code to do the muxing in PWM registers. So, lets club all pinmux handling in the same per pin mux handling code. Signed-off-by:
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Manivannan Sadhasivam authored
Earlier, the PWM registers were included as part of the pinctrl memory map, but this turned to be useless as the muxing is being handled by the SoC pin controller itself. So, lets modify the pinctrl memory map to reflect the same. Fixes: 07b734fb ("dt-bindings: pinctrl: Add BM1880 pinctrl binding") Signed-off-by:
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Jerome Brunet authored
Add pinconf support for PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_OUTPUT in the meson pinctrl driver. Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
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Jerome Brunet authored
add support for the pinconf DT property output-enable, output-disable, output-low and output-high in the meson pinctrl driver. Signed-off-by:
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Alexandre Torgue authored
Convert the STM32 pinctrl binding to DT schema format using json-schema. Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com> Reviewed-by:
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Alexandre Torgue authored
GPIOs are split between several banks (A, B, ...) and each bank can have up to 16 lines. Those GPIOs could be used as interrupt lines thanks to exti lines. As there are only 16 exti lines, a mux is used to select which gpio line is connected to which exti line. Mapping is done as follow: -A0, B0, C0.. -->exti_line_0 (X0 selected by mux_0) -A1, B1, C1.. -->exti_line_1 (X1 selected by mux_1) ... This patch adds a protection to avoid overriding on mux_n for exti_line_n. Signed-off-by:
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Alexandre Torgue authored
Apply suspend/resume management for stm32mp157c MPU. Signed-off-by:
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Alexandre Torgue authored
During power sequence, GPIO hardware registers could be lost if the power supply is switched off. Each device using pinctrl API is in charge of managing pins during suspend/resume sequences. But for pins used as gpio or irq stm32 pinctrl driver has to save the hardware configuration. Signed-off-by:
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Linus Walleij authored
Hogs would create circular device links, so do not link the device to itself. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by:
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- May 23, 2019
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Benjamin Gaignard authored
Set create_link to inform pinctrl core that stmfx wants to create link with its consumers. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by:
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Benjamin Gaignard authored
A pin controller may want to create a link between itself and its clients to be sure of suspend/resume call ordering. Introduce link_consumers field in pinctrl_desc structure to let pinctrl core knows that controller expect to create a link. Signed-off-by:
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Doug Berger authored
ARCH_BRCMSTB needs to use the BCM2835 pin controller for chips like BCM7211 which adopted that pin controller for GPIO. This commit makes the option menu configurable with default enabled for ARCH_BRCMSTB and ARCH_BCM2835. Signed-off-by:
Doug Berger <opendmb@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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Florian Fainelli authored
BCM7211 has a slightly different block layout and some additional GPIO registers that were added, document the compatible string. Signed-off-by:
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Guillaume La Roque authored
add drive-strength bank regiter and bit value for G12A SoC Signed-off-by:
Guillaume La Roque <glaroque@baylibre.com> Reviewed-by:
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Guillaume La Roque authored
drive-strength-microamp is a new feature needed for G12A SoC. the default DS setting after boot is usually 500uA and it is not enough for many functions. We need to be able to set the drive strength to reliably enable things like MMC, I2C, etc ... Signed-off-by:
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Guillaume La Roque authored
rework bias enable/disable part to prepare drive-strength integration no functional changes Signed-off-by:
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Guillaume La Roque authored
Add optional drive-strength-microamp property Signed-off-by:
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Guillaume La Roque authored
Add drive-strength-microamp property support to allow drive strength in uA Signed-off-by:
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Guillaume La Roque authored
This property allow drive-strength parameter in uA instead of mA. Signed-off-by:
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Wen Yang authored
The call to of_parse_phandle returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./drivers/pinctrl/pinctrl-rockchip.c:3221:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 3196, but without a corresponding object release within this function. ./drivers/pinctrl/pinctrl-rockchip.c:3223:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 3196, but without a corresponding object release within this function. Signed-off-by:
Wen Yang <wen.yang99@zte.com.cn> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-gpio@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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