clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate independently. We never had an issue so far because these clocks were provided 'enabled' by the bootloader. Add these gates to enable/disable the clocks when required. Signed-off-by:Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com>
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- drivers/clk/meson/axg.c 85 additions, 10 deletionsdrivers/clk/meson/axg.c
- drivers/clk/meson/axg.h 6 additions, 1 deletiondrivers/clk/meson/axg.h
- drivers/clk/meson/gxbb.c 90 additions, 10 deletionsdrivers/clk/meson/gxbb.c
- drivers/clk/meson/gxbb.h 6 additions, 1 deletiondrivers/clk/meson/gxbb.h
- drivers/clk/meson/meson8b.c 85 additions, 10 deletionsdrivers/clk/meson/meson8b.c
- drivers/clk/meson/meson8b.h 6 additions, 1 deletiondrivers/clk/meson/meson8b.h
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