- Jan 25, 2019
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Timo Alho authored
This patch adds driver for Tegra210 BPMP firmware. The BPMP is a specific processor in Tegra210 chip, which runs firmware for assisting in entering deep low power states (suspend to ram), and offloading DRAM memory clock scaling on some platforms. Based on work by Sivaram Nair <sivaramn@nvidia.com> Signed-off-by:
Timo Alho <talho@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Timo Alho authored
Split BPMP driver into common and chip specific parts to facilitate adding support for previous and future Tegra chips that are using BPMP as co-processor. Signed-off-by:
Timo Alho <talho@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Jon Hunter authored
Now there are no more external users of tegra_powergate_is_powered(), make this a local function. Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Jan 16, 2019
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Dmitry Osipenko authored
The device-tree binding has been changed. There is no separate GART device anymore, it is squashed into the Memory Controller. Integrate GART module with the MC in a way it is done for the SMMU on Tegra30+. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
Joerg Roedel <jroedel@suse.de>
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Dmitry Osipenko authored
The tegra20-mc device-tree binding has been changed, GART has been squashed into Memory Controller and now the clock property is mandatory for Tegra20, the DT compatible has been changed as well. Adapt driver to the DT changes. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Joerg Roedel <jroedel@suse.de>
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- Jan 11, 2019
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Ioana Ciocoi Radulescu authored
In all QBMan registers, the buffer pool id field is two bytes long. The low level qbman APIs reflect this, but the high level DPIO ones use u32. Modify them in order to avoid implicit downcasts. Signed-off-by:
Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by:
Li Yang <leoyang.li@nxp.com>
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Ioana Ciornei authored
Automatically add a device link between the actual device requesting the dpaa2_io_service_register and the underlying dpaa2_io used. This link will ensure that when a DPIO device, which is indirectly used by other devices, is unbound any consumer devices will be also unbound from their drivers. For example, any DPNI, bound to the dpaa2-eth driver, which is using DPIO devices will be unbound before its supplier device. Also, add a new parameter to the dpaa2_io_service_[de]register functions to specify the requesting device (ie the consumer). Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Horia Geanta <horia.geanta@nxp.com> Reviewed-by:
Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by:
Li Yang <leoyang.li@nxp.com>
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Ioana Ciornei authored
Add a new field in the dpaa2_io structure to hold a backpointer to the actual DPIO device. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by:
Li Yang <leoyang.li@nxp.com>
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- Jan 09, 2019
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Stefan Wahren authored
Add latest firmware property tags from the latest Raspberry Pi downstream kernel. This is needed to use the reboot notify in the following commit. Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
Eric Anholt <eric@anholt.net>
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- Jan 08, 2019
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Ioana Ciornei authored
The current implementation of the dpio driver uses a static next_cpu variable to keep track of the index of the next cpu available. This approach does not handle well unbinding and binding dpio devices in a random order. For example, unbinding a dpio and then binding it again with the driver, will generate the below error: $ echo dpio.5 > /sys/bus/fsl-mc/drivers/fsl_mc_dpio/unbind $ echo dpio.5 > /sys/bus/fsl-mc/drivers/fsl_mc_dpio/bind [ 103.946380] fsl_mc_dpio dpio.5: probe failed. Number of DPIOs exceeds NR_CPUS. [ 103.955157] fsl_mc_dpio dpio.5: fsl_mc_driver_probe failed: -34 -bash: echo: write error: No such device Fix this error by keeping a global cpumask of unused cpus that will be updated at every dpaa2_dpio_[probe,remove]. Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by:
Li Yang <leoyang.li@nxp.com>
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- Dec 19, 2018
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Roy Pledge authored
Add FQ (Frame Queue) and BP (Buffer Pool) query APIs that users of QBMan can invoke to see the status of the queues and pools that they are using. Signed-off-by:
Roy Pledge <roy.pledge@nxp.com> Signed-off-by:
Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- Dec 14, 2018
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Jon Hunter authored
When CONFIG_SMP is disabled, the tegra clk driver now fails to build: drivers/clk/tegra/clk-tegra30.c: In function ‘tegra30_cpu_rail_off_ready’: drivers/clk/tegra/clk-tegra30.c:1151:2: error: implicit declaration of function ‘tegra_pmc_cpu_is_powered’ [-Werror=implicit-function-declaration] cpu_pwr_status = tegra_pmc_cpu_is_powered(1) || ^ Fix the above error by removing the CONFIG_SMP ifdef around the declaration around the PMC CPU APIs because although these are not needed for non-SMP configurations, there is no harm in including these for non-SMP builds either. Fixes: 61866523ed6e ("clk: tegra30: Use Tegra CPU powergate helper function") Reported-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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- Nov 28, 2018
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Thierry Reding authored
The PMC controller on Tegra194 has a couple of new I/O pads and drops others compared to Tegra186. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Nov 23, 2018
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Madalin Bucur authored
Check that the values received by the portal interrupt coalesce change APIs are in range. Signed-off-by:
Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by:
Roy Pledge <roy.pledge@nxp.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- Nov 21, 2018
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Stefan Wahren authored
Adopt the SPDX license identifier headers to ease license compliance management. Cc: Eric Anholt <eric@anholt.net> Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
Eric Anholt <eric@anholt.net>
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- Nov 14, 2018
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Stephen Boyd authored
Let's change the function signature to return the pointer to memory or an error pointer on failure, and take an argument that lets us return the size of the aux data read. This way we can remove the cmd_db_read_aux_data_len() API entirely and also get rid of the memcpy operation from cmd_db to the caller. Updating the only user of this code shows that making this change allows us to remove a function and put the lookup where the user is. Cc: Mahesh Sivasubramanian <msivasub@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Evan Green <evgreen@chromium.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Rob Clark <robdclark@gmail.com> Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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- Nov 13, 2018
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Bo Yan authored
The function tegra_read_chipid() is declared twice in fuse.h. Remove the redundant declaration. Signed-off-by:
Bo Yan <byan@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Nov 08, 2018
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Timo Alho authored
Update the firmware header file to a more recent version. The major changes in the new version are: * add a new MRQ for firmware version query ABI and deprecates the old * add ABI to query Tegra194 CPU frequency limits * add ABI to control subset of PCIE UPHY state The new header contains also some editorial changes to the documentation. Signed-off-by:
Timo Alho <talho@nvidia.com> Acked-by:
Sivaram Nair <sivaramn@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Timo Alho authored
Add a helper function to check that firmware is supporting a given MRQ command. Signed-off-by:
Timo Alho <talho@nvidia.com> Acked-by:
Sivaram Nair <sivaramn@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Oct 23, 2018
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Mathias Thore authored
Extract error information from rx and tx buffer descriptors, and update error counters. Signed-off-by:
Mathias Thore <mathias.thore@infinera.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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- Oct 05, 2018
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Quentin Schulz authored
Since HSIO address space can be accessed by different drivers, let's simplify the register address definitions so that it can be easily used by all drivers and put the register address definition in the include/soc/mscc/ocelot_hsio.h header file. Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Acked-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Quentin Schulz authored
Since HSIO address space can be used by different drivers (PLL, SerDes muxing, temperature sensor), let's move it somewhere it can be included by all drivers. Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Acked-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Madalin Bucur authored
Add the APIs required to control the QMan portal interrupt coalescing settings. Signed-off-by:
Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by:
Li Yang <leoyang.li@nxp.com>
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- Sep 27, 2018
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Laurentiu Tudor authored
Add a couple of new APIs to check the probing status of qman and bman: 'int bman_is_probed()' and 'int qman_is_probed()'. They return the following values. * 1 if qman/bman were probed correctly * 0 if qman/bman were not yet probed * -1 if probing of qman/bman failed Drivers that use qman/bman driver services are required to use these APIs before calling any functions exported by qman or bman drivers or otherwise they will crash the kernel. The APIs will be used in the following couple of qbman portal patches and later in the series in the dpaa1 ethernet driver. Signed-off-by:
Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by:
Li Yang <leoyang.li@nxp.com>
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- Sep 21, 2018
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Horia Geantă authored
Add support for Congestion State Change Notifications (CSCN), which allow DPIO users to be notified when a congestion group changes its state (due to hitting the entrance / exit threshold). Acked-by:
Li Yang <leoyang.li@nxp.com> Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Horia Geantă authored
Add support for dpaa2_fd_list format, i.e. dpaa2_fl_entry structure and accessors. Frame list entries (FLEs) are similar, but not identical to FDs: + "F" (final) bit - FMT[b'01] is reserved - DD, SC, DROPP bits (covered by "FD compatibility" field in FLE case) - FLC[5:0] not used for stashing Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Acked-by:
Li Yang <leoyang.li@nxp.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Horia Geantă authored
This commit adds back functions removed in commit a211c817 ("staging: fsl-mc/dpio: remove couple of unused functions") since dpseci object will make use of them. Acked-by:
Li Yang <leoyang.li@nxp.com> Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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- Aug 27, 2018
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Aapo Vienamo authored
Make tegra_io_pad_set_voltage() and tegra_io_pad_get_voltage() static and remove the prototypes from pmc.h. Remove enum tegra_io_pad_voltage and use the defines from <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> instead. These functions aren't used outside of the pmc driver and new use cases should use the pinctrl interface instead. Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Aapo Vienamo authored
Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Jul 24, 2018
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Roy Pledge authored
Move the NXP DPIO (Datapath I/O Driver) out of the drivers/staging directory and into the drivers/soc/fsl directory. The DPIO driver enables access to Queue and Buffer Manager (QBMAN) hardware on NXP DPAA2 devices. This is a prerequisite to moving the DPAA2 Ethernet driver out of staging. Signed-off-by:
Roy Pledge <roy.pledge@nxp.com> Reviewed-by:
Horia Geantă <horia.geanta@nxp.com> Reviewed-by:
Ioana Radulescu <ruxandra.radulescu@nxp.com> Signed-off-by:
Li Yang <leoyang.li@nxp.com>
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- Jul 21, 2018
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Lina Iyer authored
Platform drivers need make a lot of resource state requests at the same time, say, at the start or end of an usecase. It can be quite inefficient to send each request separately. Instead they can give the RPMH library a batch of requests to be sent and wait on the whole transaction to be complete. rpmh_write_batch() is a blocking call that can be used to send multiple RPMH command sets. Each RPMH command set is set asynchronously and the API blocks until all the command sets are complete and receive their tx_done callbacks. Signed-off-by:
Lina Iyer <ilina@codeaurora.org> Signed-off-by:
Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Lina Iyer authored
Platform drivers that want to send a request but do not want to block until the RPMH request completes have now a new API - rpmh_write_async(). The API allocates memory and send the requests and returns the control back to the platform driver. The tx_done callback from the controller is handled in the context of the controller's thread and frees the allocated memory. This API allows RPMH requests from atomic contexts as well. Signed-off-by:
Lina Iyer <ilina@codeaurora.org> Signed-off-by:
Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Lina Iyer authored
Active state requests are sent immediately to the RSC controller, while sleep and wake state requests are cached in this driver to avoid taxing the RSC controller repeatedly. The cached values will be sent to the controller when the rpmh_flush() is called. Generally, flushing is a system PM activity and may be called from the system PM drivers when the system is entering suspend or deeper sleep modes during cpuidle. Also allow invalidating the cached requests, so they may be re-populated again. Signed-off-by:
Lina Iyer <ilina@codeaurora.org> [rplsssn: remove unneeded semicolon, address line over 80chars error] Signed-off-by:
Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Reviewed-by:
Evan Green <evgreen@chromium.org> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Lina Iyer authored
Sending RPMH requests and waiting for response from the controller through a callback is common functionality across all platform drivers. To simplify drivers, add a library functions to create RPMH client and send resource state requests. rpmh_write() is a synchronous blocking call that can be used to send active state requests. Signed-off-by:
Lina Iyer <ilina@codeaurora.org> Signed-off-by:
Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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Lina Iyer authored
Add controller driver for QCOM SoCs that have hardware based shared resource management. The hardware IP known as RSC (Resource State Coordinator) houses multiple Direct Resource Voter (DRV) for different execution levels. A DRV is a unique voter on the state of a shared resource. A Trigger Control Set (TCS) is a bunch of slots that can house multiple resource state requests, that when triggered will issue those requests through an internal bus to the Resource Power Manager Hardened (RPMH) blocks. These hardware blocks are capable of adjusting clocks, voltages, etc. The resource state request from a DRV are aggregated along with state requests from other processors in the SoC and the aggregate value is applied on the resource. Some important aspects of the RPMH communication - - Requests are <addr, value> with some header information - Multiple requests (upto 16) may be sent through a TCS, at a time - Requests in a TCS are sent in sequence - Requests may be fire-n-forget or completion (response expected) - Multiple TCS from the same DRV may be triggered simultaneously - Cannot send a request if another request for the same addr is in progress from the same DRV - When all the requests from a TCS are complete, an IRQ is raised - The IRQ handler needs to clear the TCS before it is available for reuse - TCS configuration is specific to a DRV - Platform drivers may use DRV from different RSCs to make requests Resource state requests made when CPUs are active are called 'active' state requests. Requests made when all the CPUs are powered down (idle state) are called 'sleep' state requests. They are matched by a corresponding 'wake' state requests which puts the resources back in to previously requested active state before resuming any CPU. TCSes are dedicated for each type of requests. Active mode TCSes (AMC) are used to send requests immediately to the resource, while control TCS are used to provide specific information to the controller. Sleep and Wake TCS send sleep and wake requests, after and before the system halt respectively. Signed-off-by:
Lina Iyer <ilina@codeaurora.org> Signed-off-by:
Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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- Jun 22, 2018
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Stefan Wahren authored
Recent Raspberry Pi firmware provides a mailbox property to detect under-voltage conditions. Here is the current definition. The u32 value returned by the firmware is divided into 2 parts: - lower 16-bits are the live value - upper 16-bits are the history or sticky value Bits: 0: undervoltage 1: arm frequency capped 2: currently throttled 16: undervoltage has occurred 17: arm frequency capped has occurred 18: throttling has occurred Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
Eric Anholt <eric@anholt.net>
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- Jun 02, 2018
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Arnd Bergmann authored
The tegra_cpuidle_pcie_irqs_in_use() function is stubbed out for non-ARM builds, but now we can compile-test the Tegra pci driver on non-Tegra ARM platforms as well, which results in a new link error: drivers/pci/host/pci-tegra.o: In function `tegra_pcie_map_irq': pci-tegra.c:(.text+0x288): undefined reference to `tegra_cpuidle_pcie_irqs_in_use' drivers/pci/host/pci-tegra.o: In function `tegra_msi_map': pci-tegra.c:(.text+0xba0): undefined reference to `tegra_cpuidle_pcie_irqs_in_use' This adapts the #ifdef statement to match the exact condition under which the function can be called. Fixes: 51bc085d ("PCI: Improve host drivers compile test coverage") Cc: Rob Herring <robh@kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- May 25, 2018
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Mahesh Sivasubramanian authored
Command DB is a simple database in the shared memory of QCOM SoCs, that provides information regarding shared resources. Some shared resources in the SoC have properties that are probed dynamically at boot by the remote processor. The information pertaining to the SoC and the platform are made available in the shared memory. Drivers can query this information using predefined strings. Signed-off-by:
Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by:
Lina Iyer <ilina@codeaurora.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
Andy Gross <andy.gross@linaro.org>
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- Apr 30, 2018
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Dmitry Osipenko authored
In order to reset busy HW properly, memory controller needs to be involved, otherwise it is possible to get corrupted memory or hang machine if HW was reset during DMA. Introduce memory client 'hot reset' that will be used for resetting of busy HW. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Dmitry Osipenko authored
Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver in a preparation for the upcoming MC hot reset controls implementation, avoiding code duplication. Note that this currently doesn't report the value of MC_GART_ERROR_REQ because it is located within the GART register area and cannot be safely accessed from the MC driver (this happens to work only by accident). The proper solution is to integrate the GART driver with the MC driver, much like is done for the Tegra SMMU, but that is an invasive change and will be part of a separate patch series. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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